H83847R Datasheet, PDF (174/719 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 5 Power-Down Modes
Bits 1 and 0: Subactive mode clock select (SA1 and SA0)
These bits select the CPU clock rate (φ_W/2, φ_W/4, or φ_W/8) in subactive mode. SA1 and SA0
cannot be modified in subactive mode.
Bit 1
SA1
0
0
1
Note:
Bit 0
SA0
Description
0
φW/8
1
φW/4
*
φW/2
* Don’t care
(initial value)
5.2 Sleep Mode
5.2.1 Transition to Sleep Mode
1. Transition to Sleep (High-Speed) Mode
The system goes from active mode to sleep (high-speed) mode when a SLEEP instruction is
executed while the SSBY and LSON bits in SYSCR1 are cleared to 0 and the MSON and DTON
bits in SYSCR2 are also cleared to 0. In sleep mode CPU operation is halted but the on-chip
peripheral functions. CPU register contents are retained.
2. Transition to Sleep (Medium-Speed) Mode
The system goes from active mode to sleep (medium-speed) mode when a SLEEP instruction is
executed while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2
is set to 1, and the DTON bit in SYSCR2 is cleared to 0. In sleep (medium-speed) mode, as in
sleep (high-speed) mode, CPU operation is halted but the on-chip peripheral functions are
operational. The clock frequency in sleep (medium-speed) mode is determined by the MA1 and
MA0 bits in SYSCR1. CPU register contents are retained.
The CPU may operate at a 1/2 state faster timing at transition to sleep (medium-speed) mode.
Rev. 6.00 Aug 04, 2006 page 138 of 680
REJ09B0145-0600