M16C Datasheet, PDF (21/39 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/26 Group
5. Electrical Characteristics (VCC=5V)
5.4 Flash Memory Version Electrical Characteristics
Table 16.4. Flash Memory Version Electrical Characteristics (Note 1) 100E/W cycle products (D3, D5, U3, U5))
Symbol
Parameter
Standard
Min.
Typ.
Max
(Note 2)
–
Erase/Write cycle (Note 3)
100(Note 4)
–
Word program time (Vcc=5.0V, Topr=25°C)
–
Block erase time
2Kbyte block
75
600
0.2
9
8Kbyte block
0.4
9
16Kbyte block
0.7
9
32Kbyte block
1.2
9
td(SR-ES) Time delay from Suspend Request until Erase Suspend
8
–
Data retention time (Note 5)
20
Unit
cycle
µs
s
s
s
s
ms
year
Table 16.5. Flash Memory Version Electrical Characteristics (Note 6) 10000 E/W cycle products (D7, D9, U7, U9)
[blockA and block B(Note 7)]
Symbol
Parameter
–
Erase/Write cycle (Note 3, 8, 9)
–
Word program time (Vcc=5.0V, Topr=25°C)
–
Block erase time(Vcc=5.0V, Topr=25°C)
(2Kbyte block)
td(SR-ES) Time delay from Suspend Request until Erase Suspend
Min.
10000(Note 4,10)
Standard
Typ.
(Note 2)
100
0.3
Max
8
Unit
cycle
µs
s
ms
Note 1: When not otherwise specified, Vcc = 2.7 to5.5V; Topr = 0 to 60 °C.
Note 2: VCC = 5V; TOPR = 25 °C.
Note 3: Definition of E/W cycle: Each block may be written to a variable number of times - up to a maximum of the total
number of distinct word addresses - for every block erase. Performing multiple writes to the same address before
an erase operation is prohibited.
Note 4: Maximum number of E/W cycles for which opration is guaranteed.
Note 5: Topr = 55°C.
Note 6: When not otherwise specified, Vcc = 2.7 to 5.5V; Topr = -40 to 85°C (D7, U7) / -20 to 85°C (D9, U9).
Note 7: Table18.5 applies for Block A or B E/W cycles > 1000. Otherwise, use Table 18.4.
Note 8: To reduce the number of E/W cycles, a block erase should ideally be performed after writing as many different
word addresses (only one time each) as possible. It is important to track the total number of block erases.
Note 9: Should erase error occur during block erase, attempt to execute clear status register command, then clock erase
command at least three times until erase error disappears.
Note 10: When Block A or B E/W cycles exceed 100 (D7, D9, U7, U9), select one wait state per block access. When FMR
17 is set to "1", one wait state is inserted per access to Block A or B - regardless of the value of PM17. Wait state
insertion during access to all other blocks, as well as to internal RAM, is controlled by PM17 - regardless of the
setting of FMR17.
Note 11: Customers desiring E/W failure rate information should contact their Renesas technical support representative.
Erase suspend
request
(interrupt request)
FMR46
td(SR-ES)
Table 16.6. Flash Memory Version Program/Erase Voltage and Read Operation Voltage Characteristics
Flash program, erase voltage
Flash read operation voltage
(at Topr = 0 to 60^oC)
VCC = 2.7 V to 5.5 V
VCC=2.7 to 5.5 V
Rev.1.00 2004.6.10 page 21 of 37
REJ09B0176-0100Z