H8S-2350 Datasheet, PDF (21/1025 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

4.7 Notes on Use of the Stack ................................................................................................. 89
Section 5 Interrupt Controller .......................................................................................... 91
5.1 Overview........................................................................................................................... 91
5.1.1 Features................................................................................................................ 91
5.1.2 Block Diagram ..................................................................................................... 92
5.1.3 Pin Configuration................................................................................................. 93
5.1.4 Register Configuration ......................................................................................... 93
5.2 Register Descriptions ........................................................................................................ 94
5.2.1 System Control Register (SYSCR) ...................................................................... 94
5.2.2 Interrupt Priority Registers A to K (IPRA to IPRK) ............................................ 95
5.2.3 IRQ Enable Register (IER) .................................................................................. 96
5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL) ..................................... 97
5.2.5 IRQ Status Register (ISR) .................................................................................... 98
5.3 Interrupt Sources ............................................................................................................... 99
5.3.1 External Interrupts................................................................................................ 99
5.3.2 Internal Interrupts................................................................................................. 101
5.3.3 Interrupt Exception Handling Vector Table......................................................... 101
5.4 Interrupt Operation............................................................................................................ 105
5.4.1 Interrupt Control Modes and Interrupt Operation ................................................ 105
5.4.2 Interrupt Control Mode 0 ..................................................................................... 109
5.4.3 Interrupt Control Mode 2 ..................................................................................... 111
5.4.4 Interrupt Exception Handling Sequence............................................................... 113
5.4.5 Interrupt Response Times .................................................................................... 114
5.5 Usage Notes ...................................................................................................................... 115
5.5.1 Contention between Interrupt Generation and Disabling ..................................... 115
5.5.2 Instructions That Disable Interrupts..................................................................... 116
5.5.3 Times when Interrupts Are Disabled.................................................................... 116
5.5.4 Interrupts during Execution of EEPMOV Instruction.......................................... 117
5.6 DTC and DMAC Activation by Interrupt.......................................................................... 117
5.6.1 Overview.............................................................................................................. 117
5.6.2 Block Diagram ..................................................................................................... 118
5.6.3 Operation ............................................................................................................. 119
Section 6 Bus Controller.................................................................................................... 121
6.1 Overview........................................................................................................................... 121
6.1.1 Features................................................................................................................ 121
6.1.2 Block Diagram ..................................................................................................... 123
6.1.3 Pin Configuration................................................................................................. 124
6.1.4 Register Configuration ......................................................................................... 125
6.2 Register Descriptions ........................................................................................................ 126
Rev. 3.00 Sep 15, 2006 page xxi of xxxiv