R32C-117A Datasheet, PDF (20/118 Pages) Renesas Technology Corp – R32C/100 Series CPU Core

R32C/117A Group
1. Overview
1.5 Pin Definitions and Functions
Tables 1.15 to 1.19 show the pin definitions and functions.
Table 1.15 Pin Definitions and Functions (1/4)
Function
Symbol
I/O
Description
Power supply
VCC, VSS
I Applicable as follows: VCC = 3.0 to 5.5 V, VSS = 0 V
Connecting pins
for decoupling
capacitor
VDC0, VDC1
A decoupling capacitor for internal voltage should be
— connected between VDC0 and VDC1
Analog power
supply
AVCC, AVSS
I
Power supply for the A/D converter. AVCC and AVSS
should be connected to VCC and VSS, respectively
Reset input
RESET
I The MCU is reset when this pin is driven low
CNVSS
CNVSS
I This pin should be connected to VSS via a resistor
Debug port
NSD
I/O
This pin is to communicate with a debugger. It should be
connected to VCC via a resistor of 1 to 4.7 k
Main clock input XIN
Main clock output XOUT
I
Input/output for the main clock oscillator. A crystal, or a
ceramic resonator should be connected between pins XIN
and XOUT. An external clock should be input at the XIN
O _{while leaving the XOUT open}
Sub clock input XCIN
Sub clock output XCOUT
I
Input/output for the sub clock oscillator. A crystal oscillator
should be connected between pins XCIN and XCOUT. An
external clock should be input at the XCIN while leaving the
O _{XCOUT open}
BCLK output
BCLK
O BCLK output
Clock output
CLKOUT
O
Output of the clock with the same frequency as low speed
clocks, f8, or f32
External interrupt INT0 to INT8
input
I ^{Input for external interrupts}
NMI input
P8_5/NMI
I Input for NMI
Key input interrupt KI0 to KI3
I Input for the key input interrupt
Bus control pins D0 to D7
I/O
Input/output of data (D0 to D7) while accessing an external
memory space with a separate bus
D8 to D15
I/O
Input/output of data (D8 to D15) while accessing an
external memory space with 16-bit or 32-bit separate bus
D16 to D31
I/O
Input/output of data (D16 to D31) while accessing an
external memory space with 32-bit separate bus
A0 to A23
O Output of address bits A0 to A23
A0/D0 to A7/D7
Output of address bits (A0 to A7) and input/output of data
I/O (D0 to D7) by time-division while accessing an external
memory space with multiplexed bus
A8/D8 to
A15/D15
Output of address bits (A8 to A15) and input/output of data
I/O (D8 to D15) by time-division while accessing an external
memory space with 16-bit or 32-bit multiplexed bus
R01DS0067EJ0120 Rev.1.20
Dec 10, 2014
Page 20 of 113