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NP50P04SLG Datasheet, PDF (2/8 Pages) Renesas Technology Corp – MOS FIELD EFFECT TRANSISTOR | |||
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NP50P04SLG
Electrical Characteristics (TA = 25°C)
Item
Symbol Min
Zero Gate Voltage Drain Current IDSS
Gate Leakage Current
Gate to Source Threshold
Voltage
Forward Transfer Admittance â1
IGSS
VGS(th)
| yfs |
â1.0
12
Drain to Source On-state
Resistance â1
RDS(on)1
RDS(on)2
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance Crss
Turn-on Delay Time
td(on)
Rise Time
tr
Turn-off Delay Time
td(off)
Fall Time
tf
Total Gate Charge
QG
Gate to Source Charge
QGS
Gate to Drain Charge
Body Diode Forward Voltage â1
QGD
VF(S-D)
Reverse Recovery Time
trr
Reverse Recovery Charge
Qrr
Note: â1. Pulsed test PW ⤠350 μs, Duty Cycle ⤠2%
Typ
â1.4
44
8.2
9.8
3800
740
500
11
15
250
150
100
13
30
0.96
50
63
Max
â1
m10
â2.5
9.6
15
5700
1120
905
24
39
505
380
150
1.5
Chapter Title
Unit
μA
μA
V
Test Conditions
VDS = â40 V, VGS = 0 V
VGS = m20 V, VDS = 0 V
VDS = VGS, ID = â250 μA
S
VDS = â10 V, ID = â25 A
mΩ VGS = â10 V, ID = â25 A
mΩ VGS = â4.5 V, ID = â25 A
pF
VDS = â10 V,
pF
VGS = 0 V,
pF f = 1 MHz
ns
VDD = â20 V, ID = â25 A,
ns
VGS = â10 V,
ns
RG = 0 Ω
ns
nC
VDD = â32 V,
nC
VGS = â10 V,
nC
ID = â50 A
V
IF = â50 A, VGS = 0 V
ns
IF = â50 A, VGS = 0 V,
nC di/dt = â100 A/μs
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
RG = 25 Ω
L
PG.
50 Ω
VDD
VGS = â20 â 0 V
â
IAS BVDSS
VDS
ID
VDD
Starting Tch
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG
PG.
VGS(â)
0
Ï
Ï = 1 μs
Duty Cycle ⤠1%
RL
VDD
VGS(â)
VGS
Wave Form
0 10%
VDS(â)
90%
VDS
VDS
Wave Form 0
td(on)
VGS
90%
90%
10% 10%
tr td(off)
tf
ton
toff
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
IG = â2 mA
RL
PG.
50 Ω
VDD
R07DS0241EJ0100 Rev.1.00
Feb 09, 2011
Page 2 of 6
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