NP50P04SLG Datasheet, PDF (1/8 Pages) Renesas Technology Corp – MOS FIELD EFFECT TRANSISTOR

NP50P04SLG
MOS FIELD EFFECT TRANSISTOR
Preliminary Data Sheet
R07DS0241EJ0100
Rev.1.00
Feb 09, 2011
Description
The NP50P04SLG is P-channel MOS Field Effect Transistor designed for high current switching applications.
Features
• Super low on-state resistance
⎯ R_DS(on)1 = 9.6 mΩ MAX. (VGS = −10 V, ID = −25 A)
⎯ R_DS(on)2 = 15 mΩ MAX. (VGS = −4.5 V, ID = −25 A)
• Low input capacitance
• Gate to Source ESD protection diode built-in
Ordering Information
Part No.
LEAD PLATING
PACKING
NP50P04SLG-E1-AY ^∗1
Pure Sn (Tin)
Tape 2500 p/reel
NP50P04SLG-E2-AY ^∗1
Note: ^∗1. Pb-free (This product does not contain Pb in external electrode.)
Package
TO-252 (MP-3ZK)
Absolute Maximum Ratings (T_A = 25°C)
Item
Drain to Source Voltage (V_GS = 0 V)
Gate to Source Voltage (V_DS = 0 V)
Drain Current (DC) (T_C = 25°C)
Drain Current (pulse) ^∗1
Total Power Dissipation (T_C = 25°C)
Total Power Dissipation (T_A = 25°C)
Channel Temperature
Storage Temperature
Single Avalanche Current ^∗2
Single Avalanche Energy ^∗2
Symbol
V_DSS
V_GSS
I_D(DC)
I_D(pulse)
P_T1
P_T2
T_ch
T_stg
I_AS
E_AS
Ratings
−40
m20
m50
m150
84
1.2
175
−55 to +175
37
136
Unit
V
V
A
A
W
W
°C
°C
A
mJ
Thermal Resistance
Channel to Case Thermal Resistance
Channel to Ambient Thermal Resistance ^∗2
R_th(ch-C)
R_th(ch-A)
1.78
°C/W
125
°C/W
Notes: ^∗1. PW ≤ 10 μs, Duty Cycle ≤ 1%
∗_{2. Starting Tch = 25°C, VDD = −20 V, RG = 25 Ω, VGS = −20 → 0 V}
R07DS0241EJ0100 Rev.1.00
Feb 09, 2011
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