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NP28N10SDE_15 Datasheet, PDF (2/8 Pages) Renesas Technology Corp – MOS FIELD EFFECT TRANSISTOR
NP28N10SDE
Chapter Title
Electrical Characteristics (TA = 25°C)
Item
Zero Gate Voltage Drain Current
Gate Leakage Current
Gate to Source Threshold Voltage
Forward Transfer Admittance ∗1
Drain to Source On-state
Resistance ∗1
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage ∗1
Reverse Recovery Time
Reverse Recovery Charge
Note: ∗1. Pulsed test
Symbol
IDSS
IGSS
VGS(th)
| yfs |
RDS(on)1
RDS(on)2
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
QG
QGS
QGD
VF(S-D)
trr
Qrr
MIN.
1.5
9
TYP.
2.0
18
41
45
2200
160
90
12
9
53
5
49
7
13
1
73
175
MAX.
10
±100
2.5
52
59
3300
240
165
39
23
106
13
75
1.5
Unit
μA
nA
V
S
mΩ
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
Test Conditions
VDS = 100 V, VGS = 0 V
VGS = ±20 V, VDS = 0 V
VDS = VGS, ID = 250 μ A
VDS = 10 V, ID = 14 A
VGS = 10 V, ID = 14 A
VGS = 4.5 V, ID = 14 A
VDS = 25 V,
VGS = 0 V,
f = 1 MHz
VDD = 50 V, ID = 14 A,
VGS = 10 V
RG = 0 Ω
VDD = 80 V,
VGS = 10 V,
ID = 28 A
IF = 28 A, VGS = 0 V
IF = 28 A, VGS = 0 V,
di/dt = 100 A/μs
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG = 25 Ω
L
PG.
50 Ω
VDD
VGS = 20 → 0 V
IAS
ID
VDD
BVDSS
VDS
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
PG.
RG
VGS
0
τ
τ = 1 μs
Duty Cycle ≤ 1%
RL
VDD
VGS
VGS
Wave Form
10%
0
VDS
90%
VDS
VDS
0
Wave Form
td(on)
VGS
90%
90%
10% 10%
tr td(off)
tf
ton
toff
D.U.T.
IG = 2 mA
RL
PG.
50 Ω
VDD
R07DS0507EJ0100 Rev.1.00
Sep 16, 2011
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