HD74LS76A Datasheet, PDF (2/7 Pages) Hitachi Semiconductor – Dual J-K Flip-Flop(with Preset and Clear)

HD74LS76A
Function Table
Inputs
Outputs
Preset
Clear
Clock
J
K
Q
Q
L
H
X
X
X
H
L
H
L
X
X
X
L
H
L
L
X
X
X
H*
H*
H
H
↓
L
L
Q0
Q0
H
H
↓
H
L
H
L
H
H
↓
L
H
L
H
H
H
↓
H
H
Toggle
H
H
H
X
X
Q0
Q0
H; high level, L; low level, X; irrelevant, ↓; transition from high to low level,
Q0; level of Q before the indicated steady-state input conditions were established.
Q0; complement of Q0 or level of Q before the indicated steady-state input conditions were established.
Toggle; each output changes to the complement of its previous level on each active transition indicated by ↓.
* This configuration is nonstable; that is, it will not persist when preset and clear inputs return to their inactive (high) level.
Block Diagram (1/2)
Q
Preset
K
Clock
Q
Clear
J
Absolute Maximum Ratings
Item
Symbol
Ratings
Supply voltage
VCC
7
Input voltage
VIN
7
Power dissipation
PT
400
Storage temperature
Tstg
–65 to +150
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Recommended Operating Conditions
Item
Supply voltage
Output current
Operating temperature
Clock frequency
Clock High
Pulse width
Clear Preset Low
Setup time
“H” Data
“L” Data
Hold time
Symbol
VCC
IOH
IOL
Topr
fclock
tw
tw
tsu
tsu
th
Min
4.75
—
—
–20
0
20
25
20↓
20↓
0↓
Typ
Max
5.00
5.25
—
–400
—
8
25
75
—
30
—
—
—
—
—
—
—
—
—
—
Unit
V
V
mW
°C
Unit
V
µA
mA
°C
MHz
ns
ns
ns
Rev.3.00, Jul.22.2005, page 2 of 6