HD74AC74 Datasheet, PDF (2/8 Pages) Hitachi Semiconductor – Dual D-Type Positive Edge-Triggered Flip-Flop

HD74AC74
Logic Symbol
S_D1
D₁
Q₁
CP₁
C_D1 ^Q1
S_D2
D₂
Q₂
CP₂
C_D2 ^Q2
Pin Names
D₁, D₂
CP₁, CP₂
C_D1, C_D2
S_D1, S_D2
Q₁, Q₁, Q₂, Q ₂
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
Truth Table (Each Half)
Inputs
S_D
L
C_D
H
CP
X
D
X
H
L
X
X
L
L
X
X
H
H
H
H
H
L
H
H
L
X
H
: High Voltage Level
L
: Low Voltage Level
X
: Immaterial
: Low-to-High Clock Transition
Q₀ (Q₀) : Previous Q (Q) before Low-to-High Transition of Clock
Logic Diagram
S_D
D
CP
Outputs
Q
Q
H
L
L
H
H
H
H
L
L
H
Q₀
Q₀
Q
Q
C_D
Please note that this diagram is provised only for the understanding of logic operations and should not be
used to estimate propagation delays.
Rev.2.00, Jul.16.2004, page 2 of 7