HD74AC74 Datasheet, PDF (1/8 Pages) Hitachi Semiconductor – Dual D-Type Positive Edge-Triggered Flip-Flop

HD74AC74
Dual D-Type Positive Edge-Triggered Flip-Flop
REJ03D0277–0200Z
(Previous ADE-205-361 (Z))
Rev.2.00
Jul.16.2004
Description
The HD74AC74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs.
Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a
voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the
Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be
transferred to the outputs until the next rising edge of the Clock Pulse input.
Features
Asynchronous Inputs:
Low input to S_D (Set) sets Q to High level
Low input to C_D (Clear) sets Q to Low level
Clear and Set are independent of clock
Simultaneous Low on C_D and S_D makes both Q and Q High
• Outputs Source/Sink 24 mA
• Ordering Information
Part Name
Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity)
HD74AC74P
DIP-14 pin
DP-14, -14AV P
—
HD74AC74FPEL SOP-14 pin (JEITA) FP-14DAV
FP
EL (2,000 pcs/reel)
HD74AC74RPEL SOP-14 pin (JEDEC) FP-14DNV
RP
EL (2,500 pcs/reel)
HD74AC74TELL TSSOP-14 pin
TTP-14DV
T
ELL (2,000 pcs/reel)
Notes: 1. Please consult the sales office for the above package availability.
2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of
the package code.
Pin Arrangement
C_D1 1
D₁ 2
CP₁ 3
S_D1 4
Q₁ 5
Q₁ 6
GND 7
CP1 D1
SD1 _CD1
Q1 Q1
D2 CP₂
CD2 SD2
Q2 Q2
(Top view)
14 V_CC
13 C_D2
12 D₂
11 CP₂
10 S_D2
9 Q₂
8 Q₂
Rev.2.00, Jul.16.2004, page 1 of 7