2SK1764 Datasheet, PDF (2/7 Pages) Hitachi Semiconductor – Silicon N-Channel MOS FET

2SK1764
Absolute Maximum Ratings
Item
Symbol
Drain to source voltage
VDSS
Gate to source voltage
VGSS
Drain current
Drain peak current
ID
ID(pulse)*1
Body to drain diode reverse drain current
IDR
Channel power dissipation
Pch*2
Channel temperature
Tch
Storage temperature
Tstg
Notes: 1. PW ≤ 100 µs, duty cycle ≤ 10 %
2. Value on the alumina ceramic board (12.5 x 20 x 0.7 mm)
Ratings
60
±20
2
4
2
1
150
–55 to +150
(Ta = 25°C)
Unit
V
V
A
A
A
W
°C
°C
Electrical Characteristics
(Ta = 25°C)
Item
Symbol Min
Typ
Max
Unit
Test Conditions
Drain to source breakdown voltage V(BR)DSS
60
Gate to source breakdown voltage V(BR)GSS ±20
Gate to source cutoff voltage
VGS(off)
1
Drain to source cutoff current
IDSS
—
Gate to source cutoff current
IGSS
—
Static drain to source on state
resistance
RDS(on)1
—
Static drain to source on state
resistance
RDS(on)2
—
Forward transfer admittance
|yfs|
0.9
Input capacitance
Ciss
—
Output capacitance
Coss
—
—
—
—
—
—
2
—
10
—
±5
0.3
0.45
0.4
0.60
1.7
—
140
—
75
—
V ID = 10 mA, VGS = 0
V IG = ±100 µA, VDS = 0
V VDS = 10 V, ID = 1 mA
µA VDS = 50 V, VGS = 0
µA VGS = ±15 V, VDS = 0
Ω
VGS = 10 V, ID = 1 A*³
Ω
VGS = 4 V, ID = 1 A*³
S
VDS = 10 V, ID = 1 A*³
pF VDS = 10 V, VGS = 0,
pF ^{f = 1 MHz}
Reverse transfer capacitance
Turn on time
Turn off time
Note: 3. Pulse Test
Crss
—
20
—
pF
ton
—
18
—
ns VDS = 10 V, ID = 1 A*³,
toff
—
80
—
ns ^RL ^{= 30 Ω}
Rev.2.00 Sep 07, 2005 page 2 of 6