PD46184184B Datasheet, PDF (18/39 Pages) Renesas Technology Corp – 18M-BIT DDR II SRAM 4-WORD BURST OPERATION

μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B
DC Characteristics 2 (TA = −40 to 85°C, VDD = 1.8 ± 0.1 V)
Parameter
Symbol
Test condition
MIN.
Input leakage current
ILI
−2
I/O leakage current
ILO
−2
Operating supply current IDD VIN ≤ VIL or VIN ≥ VIH,
-E33Y
(Read cycle / Write cycle)
II/O = 0 mA, Cycle = MAX.
-E40Y
MAX.
Unit Note
x8 x9 x18 x36
+2
μA
+2
μA
640 640 710 870 mA
580 580 650 780
Standby supply current
(NOP)
ISB1 VIN ≤ VIL or VIN ≥ VIH,
-E33Y
II/O = 0 mA, Cycle = MAX.
Inputs static
-E40Y
510 510 520 550 mA
490 490 500 520
Output HIGH voltage
Output LOW voltage
VOH(Low) |IOH| ≤ 0.1 mA
VOH Note1
VOL(Low) IOL ≤ 0.1 mA
VOL Note2
VDDQ − 0.2
VDDQ/2−0.12
VSS
VDDQ/2−0.12
VDDQ
VDDQ/2+0.12
0.2
VDDQ/2+0.12
V 3, 4
V 3, 4
V 3, 4
V 3, 4
Notes 1. Outputs are impedance-controlled. | I_OH | = (V_DDQ/2)/(RQ/5) ±15% for values of 175 Ω ≤ RQ ≤ 350 Ω.
2. Outputs are impedance-controlled. I_OL = (V_DDQ/2)/(RQ/5) ±15% for values of 175 Ω ≤ RQ ≤ 350 Ω.
3. AC load current is higher than the shown DC values.
4. HSTL outputs meet JEDEC HSTL Class I standards.
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 18 of 38