PD46184184B Datasheet, PDF (14/39 Pages) Renesas Technology Corp – 18M-BIT DDR II SRAM 4-WORD BURST OPERATION

μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B
[μPD46185364B]
Operation
Write D0 to D35
Write D0 to D8
Write D9 to D17
Write D18 to D26
Write D27 to D35
Write nothing
K
L→H
−
L→H
−
L→H
−
L→H
−
L→H
−
L→H
−
K#
−
L→H
−
L→H
−
L→H
−
L→H
−
L→H
−
L→H
BW0#
0
0
0
0
1
1
1
1
1
1
1
1
BW1#
0
0
1
1
0
0
1
1
1
1
1
1
BW2#
0
0
1
1
1
1
0
0
1
1
1
1
BW3#
0
0
1
1
1
1
1
1
0
0
1
1
Remarks 1. H : HIGH, L : LOW, → : rising edge.
2. Assumes a WRITE cycle was initiated. BW0# to BW3# can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 14 of 38