6V7 Datasheet, PDF (164/298 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Notes 1 : Set up the amplitude inputted from CVIN pin to satisfy the following conditions.
(1) Set up as below :
input amplitude + synchronized chip clamp potential < VCCi + 0.3 V.
Vcci shows Vcci power supply pin voltage.
Sink tip clamp pin serves as (43/120) x VCCi .
Example) In the case of VCCi = 3.3V input amplitude = 2.0V
2.0V + 1.18 V = 3.18 V < 3.6 V = 3.3 V + 0.3 V
(2) Each signal level to input amplitude of CVIN pin is shown in Figure 2.14.2.
White level
ID1 data
max
CC data
max
Pedestal
synchronized
chip
A : 140 IRE = CVIN input amplitude
D : 70IRE
B : 50IRE
C : 40IRE
Example) When it inputs by 1.75Vpp(s) from CVIN pin, each level becomes the following.
A = 140 IRE = 1.75 V
B = 50 IRE = 1.75 x (50/140) = 0.625 V
C = 40 IRE = 1.75 x (40/140) = 0.5 V
D = 70 IRE = 1.75 x (70/140) = 0.875 V
Figure 2.14.2 Each signal level to input amplitude of CVIN pin
Notes 2 : External each constant shown in Figure 2.14.1 is an example, and is greatly influenced by video
signal output impedance, substrate capacity, etc. on a system. Evaluate input amplitude and
external each constant perfectly, and determine it.
2.14.1 Notes when not Using Data Slicer
When bit 0 of data slicer control register 1 (address 026016/030016) is “0,” terminate the pins as shown in
Figure 2.14.3
<When data slicer circuit and timing signal generating circuit is in OFF state>
Pull-down HLF pin and VHOLD pin to
Vss through a resistor of 5 kΩ or more.
Pull-up CVIN pin to Vcc through
a resistor of 5 kΩ or more.
VCCI
5 kΩ or more
HLF/HLF2
VHOLD/VHOLD2
CVIN/CVIN2
Figure 2.14.3 Termination of data slicer input/output pins when data slicer circuit and timing
generating circuit is in OFF state
Rev.1.00 May 18, 2004 page 164 of 296