6V7 Datasheet, PDF (117/298 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.11.3 Clock Asynchronous Serial I/O (UART) Mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer
data format. Tables 2.11.5 and 2.11.6 list the specifications of the UART mode. Figure 2.11.20 and
2.11.21 show the UARTi transmit/receive mode register in UART mode.
Table 2.11.5 Specifications of UART Mode (1)
Item
Transfer data format
Transfer clock
Transmission/reception control
Transmission start condition
Reception start condition
Interrupt request
generation timing
Error detection
Specification
• Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected
• Start bit: 1 bit
• Parity bit: Odd, even, or nothing as selected
• Stop bit: 1 bit or 2 bits as selected
• When internal clock is selected (bit 3 at addresses 03A016, 037816 = “0”) :
fi/16(n+1) (Note 1) fi = f1, f8, f32
• When external clock is selected (bit 3 at addresses 03A016, 037816 =“1”) :
fEXT/16(n+1)(Note 1) (Note 2)
_______
_______
_______ _______
• CTS function/RTS function/CTS, RTS function chosen to be invalid
• To start transmission, the following requirements must be met:
Transmit enable bit (bit 0 at addresses 03A516, 037D16) = “1”
Transmit buffer empty flag (bit 1 at addresses 03A516, 037D16) = “0”
_______
_______
When CTS function selected, CTS input level = “L”
• To start reception, the following requirements must be met:
Receive enable bit (bit 2 at addresses 03A516, 037D16) = “1”
Start bit detection
• When transmitting
Transmit interrupt cause select bits (bits 0 at address 03B016, bit4 at
address 037D16) = “0”: Interrupts requested when data transfer from UARTi
transfer buffer register to UARTi transmit register is completed
Transmit interrupt cause select bits (bits 0 at address 03B016, bit4 at
address 037D16) = “1”: Interrupts requested when data transmission from
UARTi transfer register is completed
• When receiving
Interrupts requested when data transfer from UARTi receive register to
UARTi receive buffer register is completed
• Overrun error (Note 3)
This error occurs when the next data is ready before contents of UARTi
receive buffer register are read out
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
This error occurs when if parity is enabled, the number of 1’s in parity and
character bits does not match the number of 1’s set
• Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is
encountered
Rev.1.00 May 18, 2004 page 117 of 296