R1LP0108E_15 Datasheet, PDF (14/17 Pages) Renesas Technology Corp – 1Mb Advanced LPSRAM (128k word x 8bit)

R1LP0108E Series
Low Vcc Data Retention Characteristics
Parameter
V_CC for data retention
Symbol Min. Typ. Max. Unit
Test conditions^*2
Vin ≥ 0V
V_DR
2.0
-
5.5
V ^{(1) 0V ≤ CS2 ≤ 0.2V or}
(2) CS1# ≥ Vcc-0.2V,
CS2 ≥ Vcc-0.2V
-
0.6^*1
2
A ~+25°C
Vcc=3.0V, Vin ≥ 0V
Data retention current
-
-
3
A ~+40°C
I_CCDR
(1) 0V ≤ CS2 ≤ 0.2V or
(2) CS1# ≥ Vcc-0.2V,
-
-
8
A ~+70°C
CS2 ≥ Vcc-0.2V
-
-
10 A ~+85°C
Chip deselect time to data retention
t_CDR
0
Operation recovery time
t_R
5
-
-
-
-
ns
ms
See retention waveform.
Note 1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 25ºC), and not 100% tested.
2. CS2 controls address buffer, WE# buffer, CS1# buffer, OE# buffer and Din buffer. If CS2 controls data
retention mode, Vin levels (address, WE#, CS1#, OE#, DQ) can be in the high impedance state.
If CS1# controls data retention mode, CS2 must be CS2 ≥ Vcc-0.2V or 0V ≤ CS2 ≤ 0.2V. The other input
levels (address, WE# ,OE#, DQ) can be in the high impedance state.
R10DS0029EJ0300 Rev.3.00
2013.6.21
Page 14 of 15