R8C2E Datasheet, PDF (111/354 Pages) Renesas Technology Corp – MCU

R8C/2E Group, R8C/2F Group
12. Interrupts
12.1.6 Interrupt Control
The following describes enabling and disabling the maskable interrupts and setting the priority for
acknowledgement. The explanation does not apply to nonmaskable interrupts.
Use the I flag in the FLG register, IPL, and bits ILVL2 to ILVL0 in each interrupt control register to enable or
disable maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each interrupt control
register.
Figure 12.3 shows the Interrupt Control Register, Figure 12.4 shows Registers TRCIC, CM0IC, and CM1IC
and Figure 12.5 shows the INTiIC Register (i=0, 1, 3).
Interrupt Control Register⁽²⁾
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TREIC
KUPIC
ADIC
S0TIC
S0RIC
TRAIC
TRBIC
Address
004Ah
004Dh
004Eh
0051h
0052h
0056h
0058h
After Reset
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
Bit Symbol
Bit Name
Function
RW
Interrupt priority level select bits ^{b2 b1 b0}
ILVL0
0 0 0 : Level 0 (interrupt disable)
RW
0 0 1 : Level 1
0 1 0 : Level 2
ILVL1
0 1 1 : Level 3
1 0 0 : Level 4
RW
1 0 1 : Level 5
ILVL2
1 1 0 : Level 6
1 1 1 : Level 7
RW
Interrupt request bit
IR
0 : Requests no interrupt
1 : Requests interrupt
RW⁽¹⁾
—
Nothing is assigned. If necessary, set to 0.
(b7-b4)
When read, the content is undefined.
—
NOTES:
1. Only 0 can be w ritten to the IR bit. Do not w rite 1.
2. Rew rite the interrupt control register w hen the interrupt request w hich is applicable for its register is not generated.
Refer to 12.6.5 Changing Interrupt Control Register Contents.
Figure 12.3 Interrupt Control Register
Rev.1.00 Dec 14, 2007 Page 95 of 332
REJ09B0349-0100