HD74HCT125 Datasheet, PDF (1/9 Pages) Hitachi Semiconductor – Quad. Bus Buffer Gates (with 3-state outputs)

HD74HCT125, HD74HCT126
Quad. Bus Buffer Gates (with 3-state outputs)
REJ03D0657–0200
(Previous ADE-205-545)
Rev.2.00
Mar 30, 2006
Description
The HD74HCT125, HD74HCT126 require the 3-state control input C to be taken high to put the output into the high
impedance condition, whereas the HD74HCT125, HD74HCT126 requires the control input to be low to put the output
into high impedance.
Features
• LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility
• High Speed Operation: t_pd (A to Y) = 12 ns typ (C_L = 50 pF)
• High Output Current: Fanout of 15 LSTTL Loads
• Wide Operating Voltage: V_CC = 4.5 to 5.5 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: I_CC (static) = 4 µA max (Ta = 25°C)
• Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
HD74HCT125P
DILP-14 pin
PRDP0014AB-B
P
(DP-14AV)
HD74HCT125FPEL
HD74HCT126FPEL
SOP-14 pin (JEITA)
PRSP0014DF-B
(FP-14DAV)
FP
HD74HCT125TELL
HD74HCT126TELL
TSSOP-14 pin
PTSP0014JA-B
T
(TTP-14DV)
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
—
EL (2,000 pcs/reel)
ELL (2,000 pcs/reel)
Function Table
Inputs
C
A
HCT125
HCT126
H
L
X
L
H
L
L
H
H
H : High level
L : Low level
X : Irrelevant
Z : Off (high-impedance) state of a 3-state output.
HCT125
Z
L
H
Output
Y
HCT126
Z
L
H
Rev.2.00 Mar 30, 2006 page 1 of 8