HYB18TC256160AF Datasheet, PDF (8/54 Pages) Qimonda AG – 256-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM

Internet Data Sheet
HYB18TC256160AF
256-Mbit Double-Data-Rate-Two SDRAM
Ball#
Name
Ball
Type
A3, E3, J3, N1, V_SS
P9
PWR
Not Connected ×16 organization
A2, E2, L1, R3, NC
NC
R7, R8
Other Balls ×16 organization
K9
ODT
I
Buffer
Type
—
—
SSTL
Function
Power Supply
Not Connected
On-Die Termination Control
Abbreviation
I
O
I/O
AI
PWR
GND
NC
Description
Standard input-only ball. Digital levels.
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
Ground
Not Connected
TABLE 6
Abbreviations for Ball Type
Abbreviation
SSTL
LV-CMOS
CMOS
OD
TABLE 7
Abbreviations for Buffer Type
Description
Serial Stub Terminated Logic (SSTL_18)
Low Voltage CMOS
CMOS Levels
Open Drain. The corresponding ball has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR.
Rev. 1.1, 2007-02
8
03062006-H3V1-XJT4