HYB18TC256160AF Datasheet, PDF (24/54 Pages) Qimonda AG – 256-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM

Internet Data Sheet
HYB18TC256160AF
256-Mbit Double-Data-Rate-Two SDRAM
975
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FIGURE 3
Differential DC and AC Input and Output Logic Levels Diagram
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5.4
Output Buffer Characteristics
This chapter describes the Output Buffer Characteristics.
TABLE 27
SSTL_18 Output DC Current Drive
Symbol
Parameter
SSTL_18
Unit
Note
I_OH
Output Minimum Source DC Current
–13.4
mA
1)2)
I_OL
Output Minimum Sink DC Current
13.4
mA
2)3)
1) V_DDQ = 1.7 V; V_OUT = 1.42 V. (V_OUT–V_DDQ) / I_OH must be less than 21 Ohm for values of V_OUT between V_DDQ and V_DDQ – 280 mV.
2) The values of I_OH(dc) and I_OL(dc) are based on the conditions given in ¹⁾ and ³⁾. They are used to test drive current capability to ensure V_IH.MIN.
plus a noise margin and V_IL.MAX minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by
shifting the desired driver operating points along 21 Ohm load line to define a convenient current for measurement.
3) V_DDQ = 1.7 V; V_OUT = 280 mV. V_OUT / I_OL must be less than 21 Ohm for values of V_OUT between 0 V and 280 mV.
TABLE 28
SSTL_18 Output AC Test Conditions
Symbol Parameter
SSTL_18
Unit
Note
V_OH
Minimum Required Output Pull-up
V_TT + 0.603
V
1)
V_OL
Maximum Required Output Pull-down
V_TT – 0.603
V
1)
V_OTR
Output Timing Measurement Reference Level
0.5 × V_DDQ
V
—
1) SSTL_18 test load for V_OH and V_OL is different from the referenced load. The SSTL_18 test load has a 20 Ohm series resistor additionally
to the 25 Ohm termination resistor into V_TT. The SSTL_18 definition assumes that ± 335 mV must be developed across the effectively 25
Ohm termination resistor (13.4 mA × 25 Ohm = 335 mV). With an additional series resistor of 20 Ohm this translates into a minimum
requirement of 603 mV swing relative to V_TT, at the ouput device (13.4 mA × 45 Ohm = 603 mV).
Rev. 1.1, 2007-02
24
03062006-H3V1-XJT4