HYB18TC256160AF Datasheet, PDF (34/54 Pages) Qimonda AG – 256-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM

Internet Data Sheet
HYB18TC256160AF
256-Mbit Double-Data-Rate-Two SDRAM
4) The output timing reference voltage level is V_TT.
5) t_RAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x t_REFI.
7.2
Component AC Timing Parameters
List of Timing Parameters Tables.
Parameter
TABLE 41
DRAM Component Timing Parameter by Speed Grade - DDR2–667
Symbol
DDR2–667
Unit
Note^{1)2)3)4)5)6)7)}
DQ output access time from CK / CK
CAS to CAS command delay
Average clock high pulse width
Average clock period
CKE minimum pulse width ( high and low pulse
width)
t_AC
t_CCD
t_CH.AVG
t_CK.AVG
t_CKE
Average clock low pulse width
Auto-Precharge write recovery + precharge time
Minimum time clocks remain ON after CKE
asynchronously drops LOW
t_CL.AVG
t_DAL
t_DELAY
DQ and DM input hold time
t_DH.BASE
DQ and DM input pulse width for each input
t_DIPW
DQS output access time from CK / CK
t_DQSCK
DQS input high pulse width
t_DQSH
DQS input low pulse width
t_DQSL
DQS-DQ skew for DQS & associated DQ signals t_DQSQ
DQS latching rising transition to associated clock t_DQSS
edges
DQ and DM input setup time
DQS falling edge hold time from CK
DQS falling edge to CK setup time
CK half pulse width
t_DS.BASE
t_DSH
t_DSS
t_HP
Data-out high-impedance time from CK / CK
t_HZ
Address and control input hold time
t_IH.BASE
Control & address input pulse width for each input t_IPW
Address and control input setup time
t_IS.BASE
DQ low impedance time from CK/CK
t_LZ.DQ
DQS/DQS low-impedance time from CK / CK
t_LZ.DQS
MRS command to ODT update delay
t_MOD
Mode register set command cycle time
t_MRD
OCD drive mode output delay
t_OIT
Min.
–450
2
0.48
3000
3
Max.
+450
—
0.52
8000
—
0.48
WR + t_nRP
t_IS + t_{CK .AVG} +
t_IH
175
0.35
–400
0.35
0.35
—
– 0.25
0.52
—
––
––
—
+400
—
—
240
+ 0.25
100
0.2
0.2
Min (t_CH.ABS,
t_CL.ABS)
—
275
0.6
200
2 x t_AC.MIN
t_AC.MIN
0
2
0
––
—
—
__
t_AC.MAX
—
—
—
t_AC.MAX
t_AC.MAX
12
—
12
ps
8)
nCK —
t_CK.AVG
ps
9)10)
—
nCK
11)
t_CK.AVG
nCK
ns
10)11)
12)13)
—
ps
t_CK.AVG
ps
t_CK.AVG
t_CK.AVG
ps
t_CK.AVG
18)19)14)
—
8)
—
—
15)
16)
ps
t_CK.AVG
t_CK.AVG
ps
17)18)19)
16)
16)
20)
ps
ps
t_CK.AVG
ps
ps
ps
ns
nCK
ns
8)21)
24)22)
—
23)24)
8)21)
8)21)
31)
—
31)
Rev. 1.1, 2007-02
34
03062006-H3V1-XJT4