HYS64T16000HU Datasheet, PDF (6/73 Pages) Qimonda AG – 240-Pin Unbuffered DDR2 SDRAM Modules

Internet Data Sheet
HYS[64/72]T[16/32/64]0xxHU–[2.5/../5]–A
Unbuffered DDR2 SDRAM Modules
2
Pin Configuration
The pin configuration of the Unbuffered DDR2 SDRAM DIMM is listed by function in Table 5 (240 pins). The abbreviations used
in columns Pin and Buffer Type are explained in Table 6 and Table 7 respectively. The pin numbering is depicted in Figure 1
for non-ECC modules (×64) and Figure 2 for ECC modules (×72).
Ball No.
Name
Clock Signals
185
137
220
186
138
221
52
171
CK0
CK1
CK2
CK0
CK1
CK2
CKE0
CKE1
NC
Control Signals
193
S0#
76
S1#
NC
192
RAS
74
CAS
73
WE
Address Signals
71
BA0
190
BA1
54
BA2
NC
Pin
Type
I
I
I
I
I
I
I
I
NC
I
I
NC
I
I
I
I
I
I
NC
Buffer
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
—
SSTL
SSTL
—
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
—
Function
TABLE 5
Pin Configuration of UDIMM
Clock Signals 2:0, Complement Clock Signals 2:0
Clock Enable Rank 1:0
Note: 2 Ranks module
Not Connected
Note: 1 Rank module
Chip Select Rank 1:0
Note: 2 Ranks module
Not Connected
Note: 1 Rank module
Row Address Strobe
Column Address Strobe
Write Enable
Bank Address Bus 1:0
Bank Address Bus 2
Greater than 512Mb DDR2 SDRAMS
Not Connected
Less than 1Gb DDR2 SDRAMS
Rev. 1.41, 2006-11
6
03062006-0GN5-WTPW