HYS64T32000HM Datasheet, PDF (4/44 Pages) Qimonda AG – 214-Pin Micro-DIMM-DDR2-SDRAM Modules

Internet Data Sheet
HYS64T[32/64]0[0/2]0HM–[3S/3.7/5]–A
Micro-DIMM DDR2 SDRAM Modules
1.2
Description
The QIMONDA HYS64T[32/64]0[0/2]0HM–[3S/3.7/5]–A
module family are Unbuffered Micro-DIMM modules
“MDIMMs” with 30 mm height based on DDR2 technology.
DIMMs are available as non-ECC modules in 32M × 64
(256 MB) and 64M × 64 (512 MB) organization and density,
intended for mounting into 214-pin mezzanine connector
sockets.
The memory array is designed with 512-Mbit Double-Data-
Rate-Two (DDR2) Synchronous DRAMs. Decoupling
capacitors are mounted on the PCB board. The DIMMs
feature serial presence detect based on a serial E²PROM
device using the 2-pin I²C protocol. The first 128 bytes are
programmed with configuration data and are write protected;
the second 128 bytes are available to the customer.
Product Type¹⁾
Compliance Code²⁾
TABLE 2
Ordering Informationfor RoHS Compliant Products
Description
SDRAM
Technology
PC2-5300
HYS64T32000HM-3S-A
256MB 1R×16 PC2–5300M–555–12–B1
1 rank, Non-ECC
512 Mbit (×16)
HYS64T64020HM-3S-A
512MB 2R×16 PC2–5300M–555–12–A1
2 ranks, Non-ECC
512 Mbit (×16)
PC2–4200
HYS64T32000HM–3.7–A
256MB 1R×16 PC2–4200M–444–12–B1
1 rank, Non-ECC
512 Mbit (×16)
HYS64T64020HM–3.7–A
512MB 2R×16 PC2–4200M–444–12–A1
2 ranks, Non-ECC
512 Mbit (×16)
PC2–3200
HYS64T32000HM–5–A
256MB 1R×16 PC2–3200M–333–12–B1
1 rank, Non-ECC
512 Mbit (×16)
HYS64T64020HM–5–A
512MB 2R×16 PC2–3200M–333–12–A1
2 ranks, Non-ECC
512 Mbit (×16)
1) All Product Type numbers end with a place code, designating the silicon die revision. Example: HYS64T32000HM–3.7–A, indicating Rev.
“A” dies are used for DDR2 SDRAM components. For all QIMONDA DDR2 module and component nomenclature see Chapter 6 of this
data sheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200M–444–12–B1”, where
4200M means Unbuffered Micro-DIMM modules with 4.26 GB/sec Module Bandwidth and “444-11” means Column Address Strobe (CAS)
latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.2 and
produced on the Raw Card “B”.
Rev. 1.11, 2006-11
4
03062006-HT1R-Z2PY