HYS64T32000HM Datasheet, PDF (15/44 Pages) Qimonda AG – 214-Pin Micro-DIMM-DDR2-SDRAM Modules

Internet Data Sheet
HYS64T[32/64]0[0/2]0HM–[3S/3.7/5]–A
Micro-DIMM DDR2 SDRAM Modules
3.3
Timing Characteristics
This chapter describes the AC characteristics.
3.3.1
Speed Grade Definitions
This chapter contains the Speed Grade Definition tables.
Speed Grade
TABLE 12
Speed Grade Definition Speed Bins for DDR2-667D, DDR2–533C and DDR2–400B
DDR2–667D
DDR2–533C
DDR2–400B
Unit Note
QAG Sort Name
–3S
–3.7
–5
CAS-RCD-RP latencies
5–5–5
4–4–4
3–3–3
t_CK
Parameter
Symbol Min. Max. Min.
Max. Min. Max. —
Clock Frequency @ CL = 3 t_CK
5
8
5
8
5
8
ns
1)2)3)4)
@ CL = 4 t_CK
3.75 8
3.75
8
5
8
ns
1)2)3)4)
@ CL = 5 t_CK
3
8
3.75
8
5
8
ns
1)2)3)4)
Row Active Time
t_RAS
45
70000 45
70000 40
70000 ns
1)2)3)4)5)
Row Cycle Time
t_RC
60
—
60
—
55
—
ns
1)2)3)4)
RAS-CAS-Delay
t_RCD
15
—
15
—
15
—
ns
1)2)3)4)
Row Precharge Time
t_RP
15
—
15
—
15
—
ns
1)2)3)4)
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0) only.
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS/DQS, RDQS/RDQS,
input reference level is the crosspoint when in differential strobe mode
3) Inputs are not recognized as valid until V_REF stabilizes. During the period before V_REF stabilizes, CKE = 0.2 x V_DDQ is recognized as low.
4) The output timing reference voltage level is V_TT.
5) t_RAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x t_REFI.
Rev. 1.11, 2006-11
15
03062006-HT1R-Z2PY