HYS72T32000HP Datasheet, PDF (34/53 Pages) Qimonda AG – 240-Pin Registered DDR2 SDRAM Modules

Internet Data Sheet
HYS72T[32/64]xxxHP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
3.4.1
Currents Test Conditions
For testing the I_DD parameters, the following timing parameters are used:
Parameter
CAS Latency
Clock Cycle Time
Active to Read or Write delay
Active to Active / Auto-Refresh command period
Active bank A to Active bank B command delay
Active to Precharge Command
Precharge Command Period
Average periodic Refresh interval
TABLE 24
I_DD Measurement Test Conditions for DDR2–667
Symbol
–3S
Unit
DDR2–667D
CL_(IDD)
5
t_CK
t_CK(IDD)
3.75
ns
t_RCD(IDD)
15
ns
t_RC(IDD)
60
ns
t_RRD(IDD)
7.5
ns
t_RAS.MIN(IDD)
45
ns
t_RAS.MAX(IDD)
70000
ns
t_RP(IDD)
15
ns
t_REFI
7.8
µs
Parameter
CAS Latency
Clock Cycle Time
Active to Read or Write delay
Active to Active / Auto-Refresh command period
Active bank A to Active bank B command delay
Active to Precharge Command
Precharge Command Period
Average periodic Refresh interval
TABLE 25
I_DD Measurement Test Conditions for DDR2–533
Symbol
–3.7
Unit
DDR2–533C
CL_(IDD)
4
t_CK
t_CK(IDD)
3.75
ns
t_RCD(IDD)
15
ns
t_RC(IDD)
60
ns
t_RRD(IDD)
7.5
ns
t_RAS.MIN(IDD)
45
ns
t_RAS.MAX(IDD)
70000
ns
t_RP(IDD)
15
ns
t_REFI
7.8
µs
Rev. 1.01, 2006-09
34
03292006-ZZHP-PR83