HYS72T64400HFD-3S-B Datasheet, PDF (27/43 Pages) Qimonda AG – 240-Pin Fully-Buffered DDR2 SDRAM Modules

Product Type
Internet Data Sheet
HYS72T[64/128/256][4/5][00/20]HFD–3S–B
Organization
512MB
1 GByte
2 GByte
×72
×72
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
Label Code
PC2–5300F–555 PC2–5300F–555 PC2–5300F–555
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1
Byte#
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
Description
HEX
t_CAS.MIN (min. CAS Latency Time)
3C
Write Recovery Values Supported (WR)
42
t_WR.MIN (Write Recovery Time)
3C
Write Latency Times Supported
72
Additive Latency Times Supported
50
t_RCD.MIN (min. RAS# to CAS# Delay)
3C
t_RRD.MIN (min. Row Active to Row Active Delay)
1E
t_RP.MIN (min. Row Precharge Time)
3C
t_RAS and t_RC Extension
00
t_RAS.MIN (min. Active to Precharge Time)
B4
t_RC.MIN (min. Active to Active / Refresh Time)
F0
t_RFC.MIN LSB (min. Refresh Recovery Time Delay)
A4
t_RFC.MIN MSB (min. Refresh Recovery Time Delay)
01
t_WTR.MIN (min. Internal Write to Read Cmd Delay)
1E
t_RTP.MIN (min. Internal Read to Precharge Cmd Delay) 1E
Burst Lengths Supported
03
Terminations Supported
07
Drive Strength Supported
01
t_REFI (avg. SDRAM Refresh Period)
C2
T_CASE.MAX Delta / ∆T_4R4W Delta
50
Psi(T-A) DRAM
7A
∆T₀ (DT0) DRAM
48
∆T_2Q (DT2Q) DRAM
2E
∆T_2P (DT2P) DRAM
36
∆T_3N (DT3N) DRAM
27
∆T_4R (DT4R) / ∆T_4R4W Sign (DT4R4W) DRAM
4C
HEX
3C
42
3C
72
50
3C
1E
3C
00
B4
F0
A4
01
1E
1E
03
07
01
C2
50
7A
48
2E
36
27
4C
HEX
3C
42
3C
72
50
3C
1E
3C
00
B4
F0
A4
01
1E
1E
03
07
01
C2
50
7A
48
2E
36
27
4C
Rev. 1.2, 2006-02
27
09142006-Q5TN-B9NE