HYS72T512022HFN-3.7-A Datasheet, PDF (24/32 Pages) Qimonda AG – 240-Pin Fully-Buffered DDR2 SDRAM Modules DDR2 SDRAM

Internet Data Sheet
HYS72T512[0/1]22HFN–3.7–A
Product Type
HYS72T512022HFN–3.7–A HYS72T512122HFN–3.7–A
Organization
4 GByte
4 GByte
×72
×72
2 Ranks (×4)
2 Ranks (×4)
Label Code
PC2–4200F–444
PC2–4200F–444
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Byte# Description
HEX
22
t_RAS and t_RC Extension
00
23
t_RAS.MIN (min. Active to Precharge Time)
B4
24
t_RC.MIN (min. Active to Active / Refresh Time)
F0
25
t_RFC.MIN LSB (min. Refresh Recovery Time Delay)
FE
26
t_RFC.MIN MSB (min. Refresh Recovery Time Delay)
01
27
t_WTR.MIN (min. Internal Write to Read Cmd Delay)
1E
28
t_RTP.MIN (min. Internal Read to Precharge Cmd Delay) 1E
29
Burst Lengths Supported
03
30
Terminations Supported
07
31
Drive Strength Supported
01
32
t_REFI (avg. SDRAM Refresh Period)
C2
33
T_CASE.MAX Delta / ∆T_4R4W Delta
51
34
Psi(T-A) DRAM
60
35
∆T₀ (DT0) DRAM
34
36
∆T_2Q (DT2Q) DRAM
1D
37
∆T_2P (DT2P) DRAM
23
38
∆T_3N (DT3N) DRAM
1E
39
∆T_4R (DT4R) / ∆T_4R4W Sign (DT4R4W) DRAM
43
40
∆T_5B (DT5B) DRAM
22
41
∆T₇ (DT7) DRAM
2A
42 - 78 Not used
00
79
FBDIMM ODT Values
12
80
Not used
00
81
Channel Protocols Supported LSB
02
82
Channel Protocols Supported MSB
00
83
Back-to-Back Access Turnaround Time
10
84
AMB Read Access Delay for DDR2-800
58
85
AMB Read Access Delay for DDR2-667
42
86
AMB Read Access Delay for DDR2-533
38
87
Psi(T-A) AMB
30
88
∆T_{Idle_0} (DT Idle_0) AMB
5E
89
∆T_{Idle_1} (DT Idle_1) AMB
76
90
∆T_{Idle_2} (DT Idle_2) AMB
60
HEX
00
B4
F0
FE
01
1E
1E
03
07
01
C2
51
60
34
1D
23
1E
43
22
2A
00
12
00
02
00
10
58
42
38
30
5B
71
60
Rev. 1.1, 2006-11
24
03292006-WK9O-3A6G