HYS72T512022HFN-3.7-A Datasheet, PDF (12/32 Pages) Qimonda AG – 240-Pin Fully-Buffered DDR2 SDRAM Modules DDR2 SDRAM

Internet Data Sheet
HYS72T512[0/1]22HFN–3.7–A
3
Basic Functionality
The Advanced Memory Buffer (AMB) reference design complies with the FB-DIMM Architecture and Protocol Specification.
3.1
Advanced Memory Buffer Functionality
The Advanced Memory Buffer will perform the following FB-
DIMM channel functions:
• Supports channel initialization procedures as defined in
the initialization chapter of the FB-DIMM Architecture and
Protocol Specification to align the clocks and the frame
boundaries, verify channel connectivity, and identify AMB
DIMM position.
• Supports the forwarding of southbound and northbound
frames, servicing requests directed to a specific AMB or
DIMM, as defined in the protocol chapter, and merging the
return data into the northbound frames.
• If the AMB resides on the last DIMM in the channel, the
AMB initializes northbound frames.
• Detects errors on the channel and reports them to the host
memory controller.
• Support the FB-DIMM configuration register set as defined
in the register chapters.
• Acts as DRAM memory buffer for all read, write, and
configuration accesses addressed to the DIMM.
• Provides a read buffer FIFO and a write buffer FIFO.
• Supports an SMBus protocol interface for access to the
AMB configuration registers.
• Provides logic to support MEMBIST and IBIST Design for
Test functions.
• Provides a register interface for the thermal sensor and
status indicator.
• Functions as a repeater to extend the maximum length of
FB-DIMM Links.
Transparent Mode for DRAM Test Support
In this mode, the Advanced Memory Buffer will provide lower
speed tester access to DRAM pins through the FB-DIMM I/O
pins. This allows the tester to send an arbitrary test pattern to
the DRAMs. Transparent mode only supports a maximum
DRAM frequency equivalent to DDR2 400. Transparent mode
functionality:
• Reconfigures FB-DIMM inputs from differential high speed
link receivers to two single ended lower speed receivers
(~200 MHz)
• These inputs directly control DDR2 Command/Address
and input data that is replicated to all DRAMs
• Uses low speed direct drive FB-DIMM outputs to bypass
high speed Parallel/Serial circuitry and provide test results
back to tester
DDR2 SDRAM Interface
• Supports DDR2 at speeds of 533MT/s
• Supports 256Mb, 512Mb and 1Gb devices in x4 and x8
configurations
• 72-bit DDR2 SDRAM memory array
3.2
Interfaces
Figure 2 illustrates the Advanced Memory Buffer and all of its
interfaces. They consist of two FB-DIMM links, one DDR2
channel and an SMBus interface. Each FB-DIMM link
connects the Advanced Memory Buffer to a host memory
controller or an adjacent FB-DIMM. The DDR2 channel
supports direct connection to the DDR2 SDRAMs on a Fully
Buffered DIMM.
Rev. 1.1, 2006-11
12
03292006-WK9O-3A6G