HYS64D32301HU Datasheet, PDF (22/39 Pages) Qimonda AG – 184-Pin Unbuffered Double Data Rate SDRAM

Internet Data Sheet
HYS[64/72]D[16/32/128]3xxHU–[5/6]–C
Unbuffered DDR SDRAM Modules
8) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
9) These parameters guarantee device timing, but they are not necessarily tested on each device.
10) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured
between V_OH(ac) and V_OL(ac).
11) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition
is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from
HIGH to LOW at this time, depending on tDQSS.
12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
Rev. 1.21, 2006-09
28
03292006-RA8T-MSZL