HYS64T256020EDL Datasheet, PDF (15/51 Pages) Qimonda AG – 200-Pin SO-DIMM DDR2 SDRAM Modules

Internet Data Sheet
3.3
AC Characteristics
HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C
SO-DIMM DDR2 SDRAM Module
3.3.1
Speed Grade Definitions
All Speed grades faster than DDR2-400B comply with DDR2-400B timing specifications(t_CK = 5ns with t_RAS = 40ns).
Speed Grade Definitions for: DDR2–800 (Table 12), DDR2–667 (Table 13) and DDR2–533C (Table 14)
Speed Grade
TABLE 12
Speed Grade Definition Speed Bins for DDR2–800
DDR2–800D
DDR2–800E
Unit Note
QAG Sort Name
–2.5F
–2.5
CAS-RCD-RP latencies
5–5–5
6–6–6
t_CK
Parameter
Symbol
Min. Max.
Min. Max.
—
Clock Frequency
@ CL = 3
t_CK
5
8
5
8
ns
1)2)3)4)
@ CL = 4
t_CK
3.75 8
3.75 8
ns
1)2)3)4)
@ CL = 5
t_CK
2.5
8
3
8
ns
1)2)3)4)
@ CL = 6
t_CK
2.5
8
2.5
8
ns
1)2)3)4)
Row Active Time
t_RAS
45
70000
45
70000
ns
1)2)3)4)5)
Row Cycle Time
t_RC
57.5 —
60
—
ns
1)2)3)4)
RAS-CAS-Delay
t_RCD
12.5 —
15
—
ns
1)2)3)4)
Row Precharge Time
t_RP
12.5 —
15
—
ns
1)2)3)4)
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0)
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
3) Inputs are not recognized as valid until V_REF stabilizes. During the period before V_REF stabilizes, CKE = 0.2 x V_DDQ is recognized as low.
4) The output timing reference voltage level is V_TT.
5) t_RAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x t_REFI.
Rev. 1.0, 2007-03
15
11212006-D34H-5W6Z