PT9120 Datasheet, PDF (9/18 Pages) Princeton Technology Corp – GPS Receiver RF Front End IC

GPS Receiver RF Front End IC
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Preliminary
PT9120
The RF application circuit shown in Typical PT9120 RF application circuit schematic has been
successfully interfaced with the PTC GPS base-band processor. Since the base-band processor
requires a 2-bit IF input, the PT9120’s SGN and MAG digital outputs are both fed to the base-band
processor. Note that the SGN and MAG output pins are only capable of driving a small load, e.g. a
typical digital input (2 to 4pF), and hence, they will drive neither a clock distribution tree nor a common
15pF oscilloscope probe. Overall performance degradation of the PT9120 caused by increased
switching noise leading to excessive power line interference may result from high capacitive loading.
This interference may be reduced by inserting series damping resistors (220 to 470Ω) at the interface
between the PT9120’s SGN and MAG outputs and the base-band processor inputs. As a rule of thumb,
PCB traces connected to the PT9120’s digital output pins should be kept short and routed away from
the external IF filter components.
CRYSTAL OSCILLATOR
The reference frequency for the PLL and the clock signal for the 2-bit A/D converter may be generated
by either the on-chip crystal oscillator, or supplied externally. An external reference clock signal (such
as the low amplitude signal from a typical TCXO as shown in the application circuit in Typical PT9120
RF application circuit schematic) should only be ac-coupled to the XO pin when the on-chip crystal
oscillator is enabled (XEN is set to TVDD) since the on-chip oscillator device will serve as a buffer for
the external signal. The external reference clock signal should have a minimum voltage swing of
400mV_P-P.
The on-chip crystal oscillator uses a Pierce topology and requires external crystal resonator and shunt
load capacitances. The crystal oscillator is enabled by setting XEN to TVDD and disabled by setting
XEN to logic LOW. The XEN pin should never be left floating. For interfacing to the PTC base-band
processor, the crystal oscillator should be set to 16.368MHz.
SUPPORTED FREQUENCY PLANS
The PT9120 supports separate frequency plans for eight different reference frequencies. The selection
of the reference frequency is determined by logic input level at the MODE pin (which should be
hardwired to either AVDD or AVSS) and also the logic levels at the internal IC metal layer M1 and M2
pads. Supported frequency plans shows the relationship among the reference frequencies,
MODE/M1/M2 logic levels, 1st and 2nd IF and LO frequencies, and N-divider divide ratios.
M1
M2
Low Low
High Low
High High
Low High
Mode
Low
High
Low
High
Low
High
Low
High
Reference
Frequency (MHz)
16.367
13.000 (GSM)
19.800(CDMA)
19.200(CDMA)
19.680 (CDMA)
14.400(PDC)
12.600(PDC)
16.367
15.360(WCDMA)
1^st IF (MHz)
20.55
16.58
24.42
23.25
15.55
18.18
21.87
20.55
18.94
2^nd IF (MHz)
4.188
3.58
4.62
4.051
4.127
3.78
3.328
4.188
3.58
Lo Frequency
(MHz)
1554.86
1592
1599.84
1552.17
1590.97
1593.6
1597.29
1554.86
1556.48
N-driver
Divide Ratio
1520
1592
1616
1536
1536
1328
1648
1520
1520
PT9120 PRE1.0
-9-
August, 2007