PT9120 Datasheet, PDF (8/18 Pages) Princeton Technology Corp – GPS Receiver RF Front End IC

GPS Receiver RF Front End IC
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Preliminary
PT9120
The IF- amplifier provides roughly 70dB of gain and includes 60dB of AGC range, which is sufficient to
accommodate a wide range of input signals without saturation. The AGC range is 2bit output of the
2-bit A/D converter as the regulation variable and sets the gain of the 1st IF amplifier to achieve a logic
HIGH duty cycle of 33% on the MAG bit output. The time constant of the AGC loop is set using a
capacitor connected to the AGCCAP pin.
DIGITAL INTERFACE
The reference clock input/output pin (CP) and the 2-bit AD converter’s digital output pins (SGN and
MAG) are CMOS-level compatible with a low-to-high logic swing from TVSS to TVDD. The SGN and
MAG outputs represent the sign and the magnitude bits, respectively, of the digitized (2-bit) 2nd IF
signal. The 4 possible levels for both SGN and MAG are coded as shown in Coded SGN and MAG
output signal.
SGN
MAG
Value
LOW
HIGH
+3
LOW
LOW
+1
HIGH
LOW
-1
HIGH
HIGH
-3
The SGN and MAG output bits change on the falling edge of CP and should be read in by the
baseband processor on the rising edge of CP as illustrated in SGN and MAG output timing diagram.
For the PT9120, the CP pin may be used as either clock input or output. With the on-chip reference
crystal oscillator enabled, the CP pin becomes an output and delivers a CMOS-level signal with a
nominal duty cycle of 50% at the same frequency as the reference crystal oscillator. By disabling the
on-chip crystal oscillator (setting XEN to logic LOW), the CP pin becomes an input which accepts an
external CMOS-level (TVSS to TVDD) clock signal with a duty cycle between 40% and 60%.
PT9120 PRE1.0
-8-
August, 2007