PT9120 Datasheet, PDF (10/18 Pages) Princeton Technology Corp – GPS Receiver RF Front End IC

GPS Receiver RF Front End IC
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Preliminary
PT9120
POWER-DOWN CONTROL
The PT9120 provides four distinct operating modes: (1) fully active, (2) stand-by, (3) doze, and (4)
sleep. CMOS-level compatible input control pins, P1 and P0, set the operating state of the chip. The
relationship between the P1 and P0 inputs and the PT9120’s operating state is given in PT9120
operating modes Gray coding has been used for the P1 and P0 inputs in order to minimize glitches
while switching from one operating mode to the other. When switching from doze to fully active mode,
stand-by should be selected first.
P1
HIGH
HIGH
LOW
LOW
P0
LOW
HIGH
HIGH
LOW
Operating Mode
Fully active
Stand-by
Doze
Sleep
POWER SUPPLY CONNECTIONS
The PT9120 minimally requires two power supply voltage connections, AVDD and TVDD. Both AVDD
and TVDD which supply voltages must be well filtered, particularly the analog power supply voltage
connection, AVDD. An R-C or L-C filter on the TVDD line may be used for improved noise suppression.
The AVDD and TVDD supply lines must also be well de-coupled. A 100nF ceramic capacitor mounted
very close to the chip package is recommended on both AVDD and TVDDTVSS. A 2.2µF (or higher)
tantalum capacitor may be required on AVDD, especially if AVDD is not regulated. In order to avoid
switching noise interference from the digital portion of the chip, it is recommended that a star grounding
topology, where AVSS and TVSS are connected at only one point very close to the chip package, be
used.
PT9120 PRE1.0
- 10 -
August, 2007