PT6555 Datasheet, PDF (6/28 Pages) Princeton Technology Corp – LCD Driver IC

PT6555
PIN DESCRIPTION
Pin Name
SG1/P1~
SG4/P4
SG5~SG39
COM1~
COM4
SG40/KS1,
SG41/KS2,
KS3 to KS6
KI1~KI5
TEST
VDD
VDD1
VDD2
VSS
OSC
DO
CE
CLK
DI
I/O Active
O
-
O
-
O
-
I
H
I
-
-
-
I
-
I
-
--
I/O -
O
-
I
H
I
I
-
Description
Segment outputs for displaying the display data
transferred by serial data input.
The SG1/P1 to SG4/P4 pins can be used as
general-purpose output ports under serial data
control.
Common driver outputs
The frame frequency f_O is given by:
f_O=(fosc/512)Hz
Key scan outputs
Although normal key scan timing lines require
diodes to be inserted in the timing lines to
prevent shorts, since these outputs are
unbalanced CMOS transistor outputs, these
outputs will not be damaged by shorting when
these outputs are used to from a key matrix. The
SG40/KS1 and SG41/KS2 pins can be used as
segment outputs when so specified by the
control data
Key scan inputs
These pins have built-in pull-down resistors.
This pin must be connected to ground.
Power supply connection. Provide a voltage of
between 4.5 and 6.0V
Used for applying the LCD drive 2/3 bias voltage
externally. Must be connected to VDD2 when a
1/2 bias drive scheme is used.
Used for applying the LCD drive 1/3 bias voltage
externally. Must be connected to VDD1 when a
1/2 bias drive scheme is used.
Power supply connection. Connect to ground.
Oscillator connection
An oscillator circuit is formed by connecting an
external resistor and capacitor at this pin.
Serial data interface connections to the
controller. Note that DO, being an open-drain
output, requires a pull-up resistor.
CE: Chip enable
CLK: Synchronization clock
DI: Transfer data
DO: Output data
Handling
when unused
Open
Open
Open
GND
-
-
Open
Open
-
VDD
Open
-
-
-
Pin No.
PT6555 PT6555-LQ
1~ 35
1~39
36~39
40~43
-
44 ~49
-
50~54
40
55
41
56
42
57
43
58
44
59
45
60
-
61
46
62
47
63
48
64
V1.1
6
August, 2009