PT6555 Datasheet, PDF (13/28 Pages) Princeton Technology Corp – LCD Driver IC

SERIAL DATA OUTPUT(ONLY PT6555-LQ)
CASE 1: CLK IS TERMINATED AT “LOW” LEVEL
PT6555
Notes:
1. Address: 43H
2. Key Output Data Bits: KD1 to KD30
3. Sleep Acknowledge Bit: SA
4. If the Key Data Read Operation is executed when DO is in “HIGH” state, then the Read Key Data Bits (KD1 to KD30) and the Sleep Acknowledge Bit
(SA) will not be valid.
5. Only PT6555-LQ has the DO pin.
CASE 2: CLK IS TERMINATED AT “HIGH” LEVEL
Notes:
1. Address: 43H
2. Key Output Data Bits: KD1 to KD30
3. Sleep Acknowledge Bit: SA
4. If the Key Data Read Operation is executed when DO is in “HIGH” state, then the Read Key Data Bits (KD1 to KD30) and the Sleep Acknowledge Bit
(SA) will not be valid.
5. Only PT6555-LQ has the DO pin.
SLEEP MODE
The Sleep Mode is enabled when any one of the Sleep Acknowledge Control Bits – S0 or S1 is set to “1”. Under the
Sleep Mode, the all the segment and common driver outputs are set to “LOW” level and the oscillation operation is
terminated. Oscillation operation will only commence again if a key is pressed. Please note that this reduces power
dissipation. The Sleep Mode is cleared when both control bits - S0 and S1 are set to “0”.
It should be noted, however, that the output pins - SG1/P1 and SG2/P2 might still be used as General Purpose Output
Ports by setting the control bits - P0 and P1 even under the Sleep Mode. In other words, the Sleep Mode does not in
anyway affect the SG1/P1 and SG2/P2 pins from being used as General Purpose Output Ports.
V1.1
13
August, 2009