PT6314 Datasheet, PDF (37/49 Pages) Texas Instruments – 3 Amp Adjustable Positive Step-down Integrated Switching Regulators

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Dot Character VFD Controller/Driver IC
PT6314
TIMING 2 REQUIREMENTS
(Unless otherwise specified, Ta=-40 To +85℃)
I80 Interface Parallel Data Transfer: Write (VDD1=5.0 ±10%)
Parameter
Symbol
Condition
Min. Typ. Max. Unit
RS hold time
tRH8
10 -
- ns
RS setup time
tRS8
10 -
- ns
System cycle time
tCYC8
168 -
- ns
Control “L” pulse width (WR) tCCLW
/WR
30 -
- ns
Control “L” pulse width (RD)
tCCLR
/RD
70 -
- ns
Control “H” pulse width (RD) tCCHW
/WR
100 -
- ns
Control “H” pulse width (RD)
tCCHR
/RD
70 -
- ns
Data setup time
tDS8
D0 to D7
55 -
- ns
Data hold time
tDH8
Do to D7
55 -
- ns
RD access time
tACC8 Do to D7, CL=100pF -
- 70 ns
Output disable time
tOH8 Do to D7, CL=100pF 5
-
- ns
Reset pulse width
tWRE
500 -
- ns
Parallel I/F (I80)
RS
tr
/C S
/W R, /RD
D0 to D7
(W R ITE )
tR S 8
tr
D0 to D7
(R E A D)
tR H S
tr
tCCLR, tCCLW
tO SS
tC Y C S
tCCHR, tCCHW
tO HS
tA C C S
tO HS
Notes:
1. Input signal rise time and fall time (tF, tR) < 15ns
2. All timing is specified using 0.20VDD1 and 0.80VDD1 as reference.
3. tCCLW and tCCLR are specified as the overlap between /CS=”L” /WR and /RD=”L”
PT6314 V1.3
- 37 -
March, 2006