PT6314 Datasheet, PDF (29/49 Pages) Texas Instruments – 3 Amp Adjustable Positive Step-down Integrated Switching Regulators

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Dot Character VFD Controller/Driver IC
“CGRAM ADDRESS SET” INSTRUCTION
PT6314
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
CODE 0 0 0 1 A A A A A A
The above instruction is used to (1) load new 6-bit address into the address counter, and (2) set the
address counter to point to the CGRAM.
Once the “CGRAM Address Set” instructions has been executed, the contents of the address counter
(ACC) is automatically modified after every access of the CGRAM, as determined by the ”Entry Mode
Set” instruction. The active width of the address counter, when it is addressing the CGRAM is 6 bits.
The counter will wrap around from 00H to 3FH if more than 64 bytes of data is written to the CGRAM.
During Reset, this instruction is irrelevant.
“DDRAM ADDRESS SET” INSTRUCTION
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
CODE 0 0 1 A A A A A A A
The above instruction is used to (1) load new 7 bits address into the address counter, and (2) set the
address counter to point to the CGRAM.
Once the “DDRAM Address Set” instruction has been executed, the contents of the address counter
(ACC) is automatically modified after every access of the DDRAM, as determined by the “Entry Mode
Set” instruction. The valid DDRAM address range is given below.
Line Display
1st Line
2nd Line
Number of
Characters
40
40
Address Range
00H to 27H
40H to 67H
During Reset, this instruction is irrelevant.
“READ BUSY FLAG AND ADDRESS” INSTRUCTION
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
CODE 0 1 BF A A A A A A A
The above instruction reads the Busy Flag (BF) * and the value of the address counter in
binary ”AAAAAAA”. This address counter is used by the CGRAM and DDRAM addresses and its
values are determined by the previous instruction. Address counter contents are the same as that of
“CGRAM Address Set” and “DDRAM Address Set” Instructions.
Note: * The Busy Flag (BF) = “0”
PT6314 V1.3
- 29 -
March, 2006