PT6584 Datasheet, PDF (23/42 Pages) Princeton Technology Corp – LCD Driver IC

LCD Driver IC
t1 t2
V DD
VDET
V LC D
CE
Inte rn al data
D1 to D56
S0 , S1, K0 , K1
P0 to P2, SC , D R
Inte rn al da ta ( D5 7 to D11 2)
Display and control data transfer
Un d e fi n ed
Un d e fi n ed
In ter nal d ata (D 113 to D 168 )
Un d e fi n ed
Tel:[phone]
Fax:[phone]
URL:http://www.princeton.com.tw
PT6584
t3 t4
VDET
V IL
Defined
Defined
Defined
Un d e fi n ed
Un d e fi n ed
Un d e fi n ed
Inte rn al data (D1 69 to D22 0)
Un d e fi n ed
S ys te m r e se t p e r io d
Defined
Un d e fi n ed
Figure 3
t1 ≥ 1 [m s] ( L o gi c bl o ck po w e r s u pp l y v ol ta g e V DD r i se ti me )
t2 ≥ 0
t3 ≥ 0
t4 ≥ 1 [m s] ( L o gi c bl o ck po w e r s u pp l y v ol ta g e V DD fa l l ti me )
PT6584 INTERNAL BLOCK STATES DURING THE RESET PERIOD
• CLOCK GENERATOR
Reset is applied and the base clock is stopped. However, the OSC pin state (normal or sleep mode)
is determined after the S0 and S1 control data bits are transferred.
• COMMON DRIVER, SEGMENT DRIVER & LATCH
Reset is applied and the display is turned off. However, display data can be input to the latch circuit
in this state.
• KEY SCAN
Reset is applied, the circuit is set to the initial state, and at the same time the key scan operation is
disabled.
• KEY BUFFER
Reset is applied and all the key data is set to low.
• CCB INTERFACE, CONTROL REGISTER, SHIFT REGISTER
Since serial data transfer is possible, these circuits are not reset.
PT6584 V1.1
- 23 -
August, 2006