PT8146 Datasheet, PDF (15/27 Pages) Princeton Technology Corp – 8-Bit 12-Ch I/O DAC

8-Bit 12-Ch I/O DAC
INPUT/OUTPUT TIMING (/CS METHOD)
t_Cr
t_CKH
t_Cf
CLK
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URL: http://www.princeton.com.tw
PT8146
SI
/CS
t_CKL
t_CSU
t_SSU t_SHD
t_SO
t_SOD
t_SOD
t_CSH
t_CCH
t_SOZ
t_PSU t_PHD
D₀ to D₁₁ (For input)
t_POD
D₀ to D₁₁ (For output)
AO₁ to AO₁₂
t_AOD
90%
10%
The decision level for CLK, SI, /CS, SO, and D0 to D3 is 80% and 20% of VCCD. The decision level for
D4 to D11 is 80% and 20% of VCCA, and for AO1 to AO12 is 90% and 10% of VCCA.
PT8146 V1.1
- 15 -
February, 2006