PT8401 Datasheet, PDF (13/28 Pages) Princeton Technology Corp – MP3 Audio Decoder

Princeton Technology Corp.
MP3 Audio Decoder
SPEECH ADPCM ENCODING TIMING
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URL: http://www.princeton.com.tw
PT8401
ALRQI2
Enc_ENA
Enc_DAT[3:0]
D1
D2
D 3 D N D N +1
D N +2
Figure 8: Speech ADPCM Encoding Timing.
In Figure 8, ALRQI2 assumes that the command register Set_SAI2 bit 0 is"0". If Bit 0 is set to "1",
the signal ALRQI2 in Figure 8 should be inverted.
I²C Microprocessor Interface
PT8401 uses I²C interface for communication. I²C communicate with multi devices using only two lines;
namely: IICD and IICC. The following control and status registers are accessible via I²C interface.
? ? S is a Start Bit (a start condition). Any transmission must start with it.
? ? Dev_addr is a 7-bit Device Address Identifier. Each device can only have one address. PT8401 is
fixed at "0110100b".
? ? R/W issues a read or write operation
? ? A/A is an Acknowledge Bit. It is performed in the receiver and is used to inform the transmitter
that the data is properly received or used to stop data transmission.
? ? P is a Stop Bit. Any sequence must end with it.
The I²C write operation is a word (two-byte) writing mode, as described in Figure 8. Multi-byte write is
PT8401 v 1.3
Page 13
Updated March 2002