PT8401 Datasheet, PDF (10/28 Pages) Princeton Technology Corp – MP3 Audio Decoder

Princeton Technology Corp.
MP3 Audio Decoder
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URL: http://www.princeton.com.tw
PT8401
PLL
PLL circuit provides two internal clocks, one for DSP and the other for the audio interface. The DSP clock
rate is twice that of the external clock while the audio interface clock rate is dependent on the external
audio clock. In order to satisfy different frequency settings, the PLL clock is divided into two sets.
PLLSet PLLfraction are used for all frequencies.
The default PLL setting assumes that the input frequency is 16.9344MHz. However, other frequency
is acceptable, too. Please refer tables below for more information. If frequency is not on the list, please
contact to PTC.
Table 1. Settings for input frequency 10 MHz.
Register Name
PLLSet
PLLFraction
Value
0x3c20
0x7f80
Table 2. Settings for input frequency 14.318MHz.
Register Name
PLLSet
PLLFraction
Value
0x3b30
0x7e88
Table 3. Settings for input frequency 14.725MHz.
Register Name
PLLSet
PLLFraction
Value
0x3930
0x7ed1
PT8401 v 1.3
Page 10
Updated March 2002