PE97022 Datasheet, PDF (6/14 Pages) Peregrine Semiconductor Corp. – 3500 MHz UltraCMOS Integer-N PLL Rad Hard for Space Applications

PE97022
Product Specification
Table 6. AC Characteristics: V_DD = 3.3 V, -40 °C < T_A < 85 °C, unless otherwise specified
Symbol
Parameter
Control Interface and Latches (see Figures 4, 5, 6)
Conditions
Min
Typical
Max
Units
f_Clk
Serial data clock frequency
(Note 1)
10
MHz
t_ClkH
Serial clock HIGH time
30
ns
t_ClkL
Serial clock LOW time
30
ns
t_DSU
Sdata set-up time after Sclk rising edge, D[7:0] set-up
time to M1_WR, M2_WR, A_WR, E_WR rising edge
10
ns
t_DHLD
Sdata hold time after Sclk rising edge, D[7:0] hold
time to M1_WR, M2_WR, A_WR, E_WR rising edge
10
ns
t_PW
S_WR, M1_WR, M2_WR, A_WR, E_WR pulse width
30
ns
Sclk rising edge to S_WR rising edge. S_WR,
t_CWR
M1_WR, M2_WR, A_WR falling edge to Hop_WR
rising edge
30
ns
t_CE
Sclk falling edge to E_WR transition
30
ns
S_WR falling edge to Sclk rising edge. Hop_WR fall-
t_WRC
ing edge to S_WR, M1_WR, M2_WR, A_WR rising
edge
30
ns
t_EC
E_WR transition to Sclk rising edge
t_MDO
MSEL data out delay after Fin rising edge
Main Divider (Including Prescaler)⁴
30
C_L = 12 pf
ns
8
ns
P_Fin
Input level range
Main Divider (Prescaler Bypassed)⁴
External AC coupling
275 MHz ≤Freq ≤3200MHz
-5
External AC coupling
3.2 GHz < Freq ≤3.5 GHz
0
3.15 V ≤V_DD ≤3.45 V
5
dBm
5
dBm
F_in
Operating frequency
50
300
MHz
P_Fin
Reference Divider
Input level range
External AC coupling
-5
5
dBm
f_r
Operating frequency
(Note 3)
100
MHz
P_fr
Reference input power²
Single-ended input
-2
10
dBm
Phase Detector
f_c
Comparison frequency
(Note 3)
SSB Phase Noise (F_in = 1.9 GHz, f_r = 20 MHz, f_c = 20 MHz, LBW = 50 kHz, V_DD = 3.3 V, Temp = 25 C)⁴
_N
Phase Noise
100 Hz Offset
_N
Phase Noise
1 kHz Offset
_N
Phase Noise
10 kHz Offset
SSB Phase Noise (F_in = 1.9 GHz, f_r = 20 MHz, f_c = 20 MHz, LBW = 50 kHz, V_DD = 3.0 V, Temp = 25 C)⁴
_N
Phase Noise
100 Hz Offset
_N
Phase Noise
1 kHz Offset
_N
Phase Noise
10 kHz Offset
-89
-95
-102
-87
-94
-101
50
MHz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Notes: 1. Fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify Fclk specification.
2. CMOS logic levels can be used to drive the reference input. If the VDD of the CMOS driver matches the VDD of PLL IC, then the reference input can be DC coupled.
Otherwise, the reference input should be AC coupled.
3. Parameter is guaranteed through characterization only and is not tested.
4. Parameters below are not tested for die sales. These parameters are verified during the element evaluation.
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Document No. 70-0235-07 │ UltraCMOS^® RFIC Solutions