PE97022 Datasheet, PDF (10/14 Pages) Peregrine Semiconductor Corp. – 3500 MHz UltraCMOS Integer-N PLL Rad Hard for Space Applications

Main Counter Chain
Normal Operating Mode
The main counter chain divides the RF input
frequency, F_in, by an integer derived from the user
-defined values in the “M” and “A” counters. It is
composed of the 10/11 dual modulus prescaler,
modulus select logic, and 9-bit M counter. Setting
Pre_en “low” enables the 10/11 prescaler. Setting
Pre_en “high” allows F_in to bypass the prescaler
and powers down the prescaler.
The output from the main counter chain, f_p, is
related to the VCO frequency, F_in, by the following
equation:
f_p = F_in / [10 x (M + 1) + A]
(1)
where A  M + 1, 1 ≤ M ≤ 511
When the loop is locked, F_in is related to the
reference frequency, f_r, by the following equation:
F_in = [10 x (M + 1) + A] x (f_r / (R+1))
(2)
where A  M + 1, 1 ≤ M ≤ 511
A consequence of the upper limit on A is that F_in
must be greater than or equal to 90 x (f_r / (R+1)) to
obtain contiguous channels. Programming the M
Counter with the minimum value of “1” will result in
a minimum M Counter divide ratio of “2”.
In Direct Interface Mode, main counter inputs M₇
and M₈ are internally forced low. In this mode, the
M value is limited to 1 ≤M ≤127.
Prescaler Bypass Mode
Setting Pre_en “high” allows F_in to bypass and
power down the prescaler. In this mode, the 10/11
prescaler and A register are not active, and the
input VCO frequency is divided by the M counter
directly. The following equation relates F_in to the
reference frequency, f_r:
F_in = (M + 1) x (f_r / (R+1)) )
(3)
where 1 ≤ M ≤ 511
In Direct Interface Mode, main counter inputs M₇
and M₈ are internally forced low. In this mode, the
M value is limited to 1 ≤M ≤127.
©2010-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 10 of 14
PE97022
Product Specification
Reference Counter
The reference counter chain divides the
reference frequency, f_r, down to the phase
detector comparison frequency, f_c.
The output frequency of the 6-bit R Counter is
related to the reference frequency by the
following equation:
f_c = f_r / (R + 1)
(4)
where 0 ≤ R ≤ 63
Note that programming R with “0” will pass the
reference frequency, f_r, directly to the phase
detector.
In Direct Interface Mode, R Counter inputs R₄
and R₅ are internally forced low (“0”). In this
mode, the R value is limited to 0 ≤R ≤15.
Register Programming
Parallel Interface Mode
Parallel Interface Mode is selected by setting the
Bmode input “low” and the Smode input “low”.
Parallel input data, D[7:0], are latched in a
parallel fashion into one of three 8-bit primary
register sections on the rising edge of M1_WR,
M2_WR, or A_WR per the mapping shown in
Table 7 on page 11. The contents of the primary
register are transferred into a secondary register
on the rising edge of Hop_WR according to the
timing diagram shown in Figure 10. Data is
transferred to the counters as shown in Table 7
on page 11.
The secondary register acts as a buffer to allow
rapid changes to the VCO frequency. This
double buffering for “ping-pong” counter control
is programmed via the FSELP input. When
FSELP is “high”, the primary register contents
set the counter inputs. When FSELP is “low”, the
secondary register contents are utilized.
Parallel input data, D[7:0], are latched into the
enhancement register on the rising edge of
E_WR according to the timing diagram shown in
Figure 10. This data provides control bits as
shown in Table 8 on page 11 with bit
functionality enabled by asserting the Enh input
“low”.
Document No. 70-0235-07 │ UltraCMOS^® RFIC Solutions