PE97022 Datasheet, PDF (3/14 Pages) Peregrine Semiconductor Corp. – 3500 MHz UltraCMOS Integer-N PLL Rad Hard for Space Applications

PE97022
Product Specification
Table 1. Pin Descriptions (continued)
Pin No. Pin Name
Interface Mode
Type
Sdata
Serial
Input
14
D₅
M₅
Sclk
Parallel
Direct
Serial
Input
Input
Input
15
D₆
Parallel
M₆
Direct
FSELS
Serial
Input
Input
Input
16
D₇
Parallel
Pre_en
Direct
Input
Input
17
GND
ALL
FSELP
Parallel
18
A₀
Direct
Serial
E_WR
19
Parallel
Input
Input
Input
Input
A₁
Direct
Input
M2_WR
Parallel
20
A₂
Direct
Input
Input
Smode
Serial, Parallel
Input
21
A₃
Direct
Input
22
Bmode
ALL
Input
23
V_DD
ALL
24
M1_WR
Parallel
(Note 1)
Input
25
A_WR
Parallel
Input
26
Hop_WR
Serial, Parallel
Input
27
F_in
ALL
Input
28
F͞_in
ALL
Input
29
GND
ALL
30
f_p
ALL
Output
Document No. 70-0235-07 │ www.psemi.com
Description
Binary serial data input. Input data entered MSB first.
Parallel data bus bit5.
M Counter bit5.
Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR
“low”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of Sclk.
Parallel data bus bit6.
M Counter bit6.
Selects contents of primary register (FSELS = 1) or secondary register (FSELS = 0)
for programming of internal counters while in Serial Interface Mode.
Parallel data bus bit7 (MSB).
Prescaler enable, active “low”. When “high”, F_in bypasses the prescaler.
Ground.
Selects contents of primary register (FSELP=1) or secondary register (FSELP = 0)
for programming of internal counters while in Parallel Interface Mode.
A Counter bit0 (LSB).
Enhancement register write enable. While E_WR is “high”, Sdata can be serially
clocked into the enhancement register on the rising edge of Sclk.
Enhancement register write. D[7:0] are latched into the enhancement register on the
rising edge of E_WR.
A Counter bit1.
M2 write. D[3:0] are latched into the primary register (R[5:4], M[8:7]) on the rising
edge of M2_WR.
A Counter bit2.
Selects serial bus interface mode (Bmode = 0, Smode = 1) or Parallel Interface Mode
(Bmode = 0, Smode = 0).
A Counter bit3 (MSB).
Selects direct interface mode (Bmode = 1).
Power supply input. Input may range from 2.85 V to 3.45 V. Bypassing
recommended.
M1 write. D[7:0] are latched into the primary register (Pre_en , M[6:0]) on the rising
edge of M1_WR.
A write. D[7:0] are latched into the primary register (R[3:0], A[3:0]) on the rising edge
of A_WR.
Hop write. The contents of the primary register are latched into the secondary
register on the rising edge of Hop_WR.
Prescaler input from the VCO, 3.5 GHz max frequency. A 22 pF coupling capacitor
should be placed as close as possible to this pin and terminated with a 50 Ω resistor
to ground.
Prescaler complementary input. A 22 pF bypass capacitor should be placed as close
as possible to this pin and be connected in series with a 50 Ω resistor to ground.
Ground.
Monitor pin for main divider output. Switching activity can be disabled through
enhancement register programming or by floating or grounding V_DD pin 31.
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