PE83336_14 Datasheet, PDF (6/12 Pages) Peregrine Semiconductor – 3000 MHz UltraCMOS® Integer-N PLL

PE83336
Product Specification
Table 6. AC Characteristics: V_DD = 3.0 V, -55° C ≤T_A ≤125° C, unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Control Interface and Latches (see Figures 4, 5, 6)
f_Clk
Serial data clock frequency
t_ClkH
Serial clock HIGH time
t_ClkL
Serial clock LOW time
t_DSU
Sdata set-up time after Sclk rising edge, D[7:0] set-up
time to M1_WR, M2_WR, A_WR, E_WR rising edge
t_DHLD
Sdata hold time after Sclk rising edge, D[7:0] hold time to
M1_WR, M2_WR, A_WR, E_WR rising edge
10
MHz
30
ns
30
ns
10
ns
10
ns
t_PW
S_WR, M1_WR, M2_WR, A_WR, E_WR pulse width
30
t_CWR
Sclk rising edge to S_WR rising edge. S_WR, M1_WR,
M2_WR, A_WR falling edge to Hop_WR rising edge
30
t_CE
Sclk falling edge to E_WR transition
30
t_WRC
S_WR falling edge to Sclk rising edge. Hop_WR falling
edge to S_WR, M1_WR, M2_WR, A_WR rising edge
30
t_EC
E_WR transition to Sclk rising edge
30
t_MDO
MSEL data out delay after Fin rising edge
C_L = 12 pf
Main Divider (Including Prescaler)
F_in
Operating frequency
500
P_Fin
Input level range
Main Divider (Prescaler Bypassed)
External AC coupling
-5
External AC coupling
85C < T_A ≤125C
0
F_in
Operating frequency
50
P_Fin
Input level range
Reference Divider
External AC coupling
-5
External AC coupling
85C < T_A ≤125C
0
f_r
Operating frequency
(Note 1)
(Note 2)
P_fr
Reference input power
V_fr
Input sensitivity
Single ended input
-2
External AC coupling
(Note 3)
0.5
Phase Detector
f_c
Comparison frequency
(Note 1)
SSB Phase Noise : Output Referred (F_in = 1918MHz, f_r = 10 MHz, f_c = 1MHz, LBW = 70 kHz)
PN_OR
Output Referred Phase Noise
100 Hz Offset:
V_DD = 3.0V, T = 25°C
-78
PN_OR
Output Referred Phase Noise
1000 Hz Offset:
V_DD = 3.0V, T = 25°C
-84
PN_OR
Output Referred Phase Noise
10000 Hz Offset:
V_DD = 3.0V, T = 25°C
-87
8 (Note 5)
3000
5
5
ns
ns
ns
ns
ns
ns
MHz
dBm
dBm
300
MHz
5
dBm
5
dBm
100
MHz
10
dBm
V_P-P
20
MHz
(Note 4)
(Note 4)
(Note 4)
dBc/Hz
dBc/Hz
dBc/Hz
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Parameter is guaranteed through characterization only and is not tested.
Running at low frequencies (< 10 MHz sinewave), the device will still be functional but may cause phase noise degradation. Inserting a low-
noise amplifier to square up the edges is recommended at lower input frequencies.
CMOS logic levels may be used if DC coupled. For optimum phase noise performance, the reference input falling edge rate should be faster
than 80mV/ns.
All devices are screened to phase noise limits listed in Table 7. The magnitude of the tester uncertainty precludes testing phase noise as
part of qualification testing. These parameters are also exempt from PDA requirements.
Parameter is tested using 100pF load capacitance and is guaranteed through characterization only. Typical test delay is 12nS.
©2010-2012 Peregrine Semiconductor Corp. All rights reserved.
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Document No. 70-0137-05 │ UltraCMOS^® RFIC Solutions
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