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PE83336_14 Datasheet, PDF (2/12 Pages) Peregrine Semiconductor – 3000 MHz UltraCMOS® Integer-N PLL
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Figure 2. Pin Configuration (Top View)
Figure 3. Package Photo
D ,M
0
0
D ,M
1
1
D ,M
2
2
D ,M
3
3
V
DD
V
DD
S_WR, D
,M
4
4
Sdata, D
,M
5
5
Sclk, D
,M
6
6
FSELS, D
, Pre_en
7
GND
6
5
4
3
2
1
44
43
42
41
40
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
17
29
18
19
20
21
22
23
24
25
26
27
28
f
c
V
_f
DD
c
PD_U
PD_D
V
DD
C
ext
V
DD
D
out
V
_f
DD
p
f
p
GND
PE83336
Product Specification
44-lead CQFJ
Table 1. Pin Descriptions
Pin No.
(44-lead
CQFJ)
Pin
Name
Interface
Mode
1
VDD
ALL
2
R0
Direct
3
R1
Direct
4
R2
Direct
5
R3
Direct
6
GND
ALL
7
D0
M0
Parallel
Direct
8
D1
M1
Parallel
Direct
9
D2
M2
Parallel
Direct
10
D3
M3
Parallel
Direct
11
VDD
ALL
12
VDD
ALL
Type
(Note 1)
Input
Input
Input
Input
(Note 1)
Input
Input
Input
Input
Input
Input
Input
Input
(Note 1)
(Note 1)
S_WR Serial
Input
13
D4
Parallel
Input
M4
Direct
Input
Description
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing recommended.
R Counter bit0 (LSB).
R Counter bit1.
R Counter bit2.
R Counter bit3.
Ground.
Parallel data bus bit0 (LSB).
M Counter bit0 (LSB).
Parallel data bus bit1.
M Counter bit1.
Parallel data bus bit2.
M Counter bit2.
Parallel data bus bit3.
M Counter bit3.
Same as pin 1.
Same as pin 1.
Serial load enable input. While S_WR is “low”, Sdata can be serially clocked. Primary register
data are transferred to the secondary register on S_WR or Hop_WR rising edge.
Parallel data bus bit4
M Counter bit4
©2010-2012 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 12
Document No. 70-0137-05 │ UltraCMOS® RFIC Solutions
Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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