PE9354 Datasheet, PDF (2/7 Pages) Peregrine Semiconductor Corp. – SPDT High Power UltraCMOS™ RF Switch Rad hard for Space Applications

Figure 3. Pin Configuration
V_DD ¹
CTRL ²
GND ³
PE9354
8 _RF1
7 _GND
6 _GND
RFC ⁴
5 _RF2
Table 2. Pin Descriptions
Pin
Pin
No.
Name
Description
1
VDD
Nominal +3V supply connection.
CMOS or TTL logic level:
2
CTRL
High = RFC to RF1 signal path
Low = RFC to RF2 signal path
Ground connection. Traces should be
3
GND
physically short and connected to
ground plane for best performance.
4
RFC
Common RF port for switch.¹
5
RF2
RF2 port.¹
Ground Connection. Traces should be
6
GND
physically short and connected to
ground plane for best performance.
Ground Connection. Traces should be
7
GND
physically short and connected to
ground plane for best performance.
8
RF1
RF1 port.¹
Note 1: All RF pins must be DC blocked with an external series
capacitor or held at 0 VDC.
Table 4. DC Electrical Specifications
Parameter
VDD Power Supply
Voltage
Input Leakage
IDD Power Supply
Current
(VDD = 3V, VCNTL = 3V)
Control Voltage High
Control Voltage Low
Min Typ
2.7
3.0
-1
Max
3.3
1
28
100
0.7xVDD
0.3xVDD
Units
V
µA
µA
V
V
©2004-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 7
PE9354
Product Specification
Table 3. Absolute Maximum Ratings
Symbol Parameter/Conditions Min Max Units
VDD
Power supply voltage
-0.3 4.0
V
VI
Voltage on any input
except for the CTRL input
-0.3
VDD+
0.3
V
VCTRL
Voltage on CTRL input
5.0
V
TST
Storage temperature range -65 150 °C
TOP
Operating temperature
range
-55 125 °C
PIN
Input power (50 Ω)
32 dBm
VESD
ESD voltage (Human Body
Model)
200
V
Total Dose
Total Cumulative Exposure
to Ionizing Radiation
100k
Rads
(Si)
Absolute Maximum Ratings are those values
listed in the above table. Exceeding these values
may cause permanent device damage.
Functional operation should be restricted to the
limits in the DC Electrical Specifications table.
Exposure to absolute maximum ratings for
extended periods may affect device reliability.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 3.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Table 5. Control Logic Truth Table
Control Voltage
CTRL = CMOS or TTL High
CTRL = CMOS or TTL Low
Signal Path
RFC to RF1
RFC to RF2
The control logic input pin (CTRL) is typically
driven by a 3-volt CMOS logic level signal, and
has a threshold of 50% of V_DD. For flexibility to
support systems that have 5-volt control logic
drivers, the control logic input has been designed
to handle a 5-volt logic HIGH signal. (A minimal
current will be sourced out of the V_DD pin when the
control logic input voltage level exceeds V_DD.)
Document No. 70-0099-02 │ UltraCMOS™ RFIC Solutions