PSM03S93E5-A Datasheet, PDF (3/11 Pages) Mitsubishi Electric Semiconductor – Dual-In-Line Package Intelligent Power Module

< Dual-In-Line Package Intelligent Power Module >
PSM03S93E5-A
TRANSFER MOLDING TYPE
INSULATED TYPE
ELECTRICAL CHARACTERISTICS (Tch = 25°C, unless otherwise noted)
INVERTER PART
Symbol
Parameter
Condition
Limits
Unit
Min. Typ. Max.
VDS(on)
VSD
ton
tC(on)
toff
tC(off)
trr
IDSS
Drain-source on-state
resistance
Source-drain voltage drop
Switching times
Drain-source cut-off
current
VD=VDB = 15V, VIN= 5V, ID= 3A
VIN= 0V, -ID= 3A
VDD= 300V, VD= VDB= 15V
ID= 3A, Tch= 125°C, VIN= 0↔5V
Inductive Load (upper-lower arm)
VDS=VDSS
Tch= 25°C
Tch= 125°C
Tch= 25°C
Tch= 125°C
-
1.50 2.00
-
3.40 4.50
Ω
-
0.90 1.30
V
0.65 1.15 1.65 μs
-
0.35 0.55 μs
-
1.00 1.50 μs
-
0.10 0.20 μs
-
0.25
-
μs
-
-
1
mA
-
-
10
CONTROL (PROTECTION) PART
Symbol
Parameter
Condition
Limits
Unit
Min. Typ. Max.
ID
Circuit current
IDB
Total of VP1-VNC, VN1-VNC
Each part of VUFB-U,
VVFB-V, VWFB-W
VD=15V, VIN=0V
VD=15V, VIN=5V
VD=VDB=15V, VIN=0V
VD=VDB=15V, VIN=5V
-
-
2.80
-
-
2.80
mA
-
-
0.10
-
-
0.10
VSC(ref)
Short circuit trip level
VD = 15V
(Note 3) 0.43
0.48
0.53
V
UVDBt
P-side Control supply
Trip level
7.0
10.0 12.0
V
UVDBr
UVDt
under-voltage protection(UV)
Tch ≤125°C
N-side Control supply
Reset level
Trip level
7.0
10.0 12.0
V
10.3
-
12.5
V
UVDr
under-voltage protection(UV)
Reset level
10.8
-
13.0
V
OTt
OTrh
Over temperature protection
(OT)
(Note4)
VD = 15V
Detect LVIC temperature
Trip level
Hysteresis of trip-reset
100
120
140 °C
-
10
-
°C
VFOH
VFOL
Fault output voltage
VSC = 0V, FO terminal pulled up to 5V by 10kΩ
VSC = 1V, IFO = 1mA
4.9
-
-
V
-
-
0.95
V
tFO
Fault output pulse width
(Note 5)
20
-
-
μs
IIN
Input current
VIN = 5V
0.70 1.00 1.50 mA
Vth(on)
ON threshold voltage
-
2.10 2.60
Vth(off)
Vth(hys)
OFF threshold voltage
ON/OFF threshold
hysteresis voltage
Applied between UP, VP, WP, UN, VN, WN-VNC
0.80 1.30
-
V
0.35 0.65
-
VF
Bootstrap Di forward voltage IF=10mA including voltage drop by limiting resistor
(Note 6) 1.1
1.7
2.3
V
R
Built-in limiting resistance Included in bootstrap Di
80
100
120
Ω
Note 3 : SC protection works for N-side only. Please select the external shunt resistance such that the SC trip-level is less than 1.7 times of the current rating.
4 : When the LVIC temperature exceeds OT trip temperature level(OTt), OT protection works and Fo outputs. In that case if the heat sink dropped off or fixed
loosely, don't reuse that DIPIPM. (There is a possibility that channel temperature of power chips exceeded maximum Tch(150°C).
5 : Fault signal Fo outputs when SC, UV or OT protection works. Fo pulse width is different for each protection modes. At SC failure, Fo pulse width is a fixed
width (=minimum 20μs), but at UV or OT failure, Fo outputs continuously until recovering from UV or OT state. (But minimum Fo pulse width is 20μs.)
6 : The characteristics of bootstrap Di is described in Fig.2.
Fig. 2 Characteristics of bootstrap Di VF-IF curve (@Ta=25°C) including voltage drop by limiting resistor (Right chart is enlarged chart.)
160
140
120
100
80
60
40
20
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
V_F [V]
30
25
20
15
10
5
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
V_F [V]
Publication Date : October 2013
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