ZY7015 Datasheet, PDF (28/34 Pages) Power-One – 3V to 13.2V Input 0.5V to 5.5V Output

ZY7015 15A DC-DC Intelligent POL Data Sheet
3V to 13.2V Input • 0.5V to 5.5V Output
R/W-1
DCL5
Bit 7
R/W-1
DCL4
R/W-1
DCL3
R/W-0
DCL2
R/W-1
DCL1
R/W-0
DCL0
R/W-0
HI
R/W-0
LO
Bit 0
Bit 7:2 DCL[5:0], Duty Cycle Limitation
00h: 0
01h: 1/64
…
3Fh: 63/64
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
Bit 1: HI, ADC high saturation feed-forward
0: disabled
1: enabled
Bit 0: LO, ADC low saturation feed-forward
0: disabled
1: enabled
Figure 53. Duty Cycle Limit Register
8.4.4 ADC Saturation Feedforward
To speed up the PWM response in case of heavy
dynamic loads, the duty cycle can be forced either to
0 or the duty cycle limit depending on the polarity of
the transient. This function is equivalent to having
two comparators defining a window around the
output voltage setpoint. When an error signal is
inside the window, it will produce gradual duty cycle
change proportional to the error signal. If the error
signal goes outside the window (usually due to large
output current steps), the duty cycle will change to its
limit in one switching cycle. In most cases this will
significantly improve transient response of the
controller, reducing amount of required external
capacitance.
Under certain circumstances, usually when the
maximum duty cycle limit significantly exceeds its
nominal value, the ADC saturation can lead to the
overcompensation of the output error. The
phenomenon manifests itself as low frequency
oscillations on the output of the POL. It can usually
be reduced or eliminated by disabling the ADC
saturation or limiting the maximum duty cycle to 120-
140% of the calculated value. It is not recommended
to use ADC saturation for output voltages higher
than 2.0V.
The ADC saturation feedforward can be
programmed in the GUI PWM Controller window or
directly via the I²C bus by writing into the DCL
register.
8.4.5 Feedback Loop Compensation
Feedback loop compensation can be programmed in
the GUI PWM Controller window by setting
frequency of poles and zeros of the transfer function.
The transfer function of the POL converter is shown
in Figure 54. It is a third order function with two
zeros and three poles. Pole 1 is the integrator pole,
Pole 2 is used in conjunction with Zero 1 and Zero 2
to adjust the phase lead and limit the gain increase
in mid band. Pole 3 is used as a high frequency low-
pass filter to limit PWM noise.
Magnitude[dB]
50
40
30
Z1 P1 Z2 P2
P3
P1: Pole 1
P2: Pole 3
P3: Pole 3
Z1: Zero 1
Z2: Zero 2
20
10
0.1
1
10
100
1000
Phase
[°]
+45
0
0.1
1
10
100
1000
-45
-90
-135
-180
Figure 54. Transfer Function of PWM
Freq
[kHz]
Freq
[kHz]
Positions of poles and zeroes are determined by
coefficients of the digital filter. The filter is
characterized by four numerator coefficients (C₀, C₁,
C₂, C₃) and three denominator coefficients (B₁, B₂,
B₃). The coefficients are automatically calculated
when desired frequency of poles and zeros is
entered in the GUI PWM Controller window. The
coefficients are stored in the C0H, C0L, C1H, C1L,
C2H, C2L, C3H, C3L, B1, B2, and B3 registers.
Note:
The GUI automatically transforms zero and pole
frequencies into the digital filter coefficients. It is strongly
recommended to use the GUI to determine the filter
coefficients.
Programming feedback loop compensation allows
optimizing POL performance for various application
conditions. For example, increase in bandwidth can
significantly improve dynamic response.
8.5 Current Share
The POL converters are equipped with the digital
current share function. To activate the current share,
interconnect the CS pins of the POLs connected in
parallel. The digital signal transmitted over the CS
ZD-00283 REV. 2.2
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