PM6341E1XC Datasheet, PDF (71/272 Pages) PMC-Sierra, Inc – E1 FRAMER/TRANSCEIVER

DATA SHEET
PMC-910419
ISSUE 8
PM6341 E1XC
E1 FRAMER/TRANSCEIVER
Jitter Characteristics
The DJAT Block provides excellent jitter tolerance and jitter attenuation while
generating minimal residual jitter. It can accommodate up to 35 UIpp of input
jitter at jitter frequencies above 9 Hz. For jitter frequencies below 9 Hz, more
correctly called wander, the tolerance increases 20 dB per decade. In most
applications the DJAT Block will limit jitter tolerance at lower jitter frequencies
only. For high frequency jitter, above 10 kHz for example, other factors such as
clock and data recovery circuitry may limit jitter tolerance and must be
considered. For low frequency wander, below 10 Hz for example, other factors
such as slip buffer hysteresis may limit wander tolerance and must be
considered. The DJAT Block meets the low frequency jitter tolerance
requirements of ITU-T Recommendation G.823.
DJAT exhibits negligible jitter gain for jitter frequencies below 8.8 Hz, and
attenuates jitter at frequencies above 8.8 Hz by 20 dB per decade. In most
applications the DJAT Block will determine jitter attenuation for higher jitter
frequencies only. Wander, below 10 Hz for example, will essentially be passed
unattenuated through DJAT. Jitter, above 10 Hz for example, will be attenuated
as specified, however, outgoing jitter may be dominated by generated residual
jitter in cases where incoming jitter is insignificant. This generated residual jitter
is directly related to the use of 24X (49.152 MHz) digital phase locked loop for
transmit clock generation. DJAT meets the jitter attenuation requirements of the
ITU-T Recommendations G.737, G.738, G.739 and G.742.
Jitter Tolerance
Jitter tolerance is the maximum input phase jitter at a given jitter frequency that a
device can accept without exceeding its linear operating range, or corrupting
data. For DJAT, the input jitter tolerance is 35 Unit Intervals peak-to-peak (UIpp)
with a worst case frequency offset of 308 Hz. It is 48 UIpp with no frequency
offset. The frequency offset is the difference between the frequency of XCLK
divided by 24 and that of the input data clock.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 55